EP0165823A2
Expired / Lapsed
EP
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Tag control circuit for buffer storage
Assignee: Fujitsu Ltd
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Filing: 1985-06-21
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Granted: —
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Expires: 2005-06-21
Abstract
Abstract A tag control circuit (300') in a memory access control apparatus in a digital computer system including a central processor (1) having a buffer storage (100), including a tag information store and update circuit (23, 30), and a circuit (24, 26, 27) for finding the necessity of operation for invalidation of the tag information and/or transmission of invalidation information to the central processor. The tag control circuit (300') includes a first circuit (40, 42, 43) storing a plurality of access requests of the necessity operation found at the necessity of operation-finding circuit, a second circuit (51, 52, 53) storing a plurality of invalidation execute information found at the necessity of operation-finding circuit, and a circuit (19') receiving a new access request and the access request stored in the first storing circuit and outputting one access request. The tag control circuit (300') may further include a third circuit (45) storing only store access requests before supplying them to the necessity of operation-finding circuit, an output of which is connected to the access request receiving and outputting circuit. The access request receiving and outputting circuit may output one access request defined by the following priority order: a new read access request, an access request stored in the first storing circuit, and a store access request stored in the third storing circuit.
Inventors
- 👤 Miyuki 7 Daiichikuruma-So Ishida
- 👤 Takashi 206 Dainisaginumagurinhira Chiba
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 04:08
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F12/00; G06F12/02; G06F12/08; G06F12/12; G06F12/121; G06F12/126; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0822; G06F2212/00; G06F2212/10; G06F2212/1032
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
237 words
A tag control circuit in a memory access control apparatus in a digital computer system including a central processor and a main storage unit,said central processor including a buffer storage temporarily storing data for use therein and another tag control circuit for managing a status of said buffer storage, and said memory access control apparatus, for processing an access request to said main storage, being provided between said central processor and said main storage, comprising: means for storing and updating tag information indicating the status of said buffer storage; means for finding a necessity of an operation for invalidation of said tag information and/or transmission of invalidation information to said central processor; first means for storing a plurality of access requests of the operation found at said of necessity/operation finding means; second means for storing a plurality of invalidation execute information found at said necessity of operation finding means corresponding to said access requests stored in said first storing means; and for means/receiving a new read access request and the access request stored in said first storing means and outputting one access request from - received/requests to said necessity / operation finding means in accordance with a predetermined priority order; said tag information storing and updating means effecting an invalidation operation and/or transmission operation of the invalidation information on said central processor in response to information stored in said necessity/operation finding means and said second storing means.
Claim 2
Dependent Claim
237 words
A tag control circuit in a memory access control apparatus in a digital computer system including a central processor and a main storage unit,said central processor including a buffer storage temporarily storing data for use therein and another tag control circuit for managing a status of said buffer storage, and said memory access control apparatus, for processing an access request to said main storage, being provided between said central processor and said main storage, comprising: means for storing and updating tag information indicating the status of said buffer storage; means for finding a necessity of an operation for invalidation of said tag information and/or transmission of invalidation information to said central processor; first means for storing a plurality of access requests of the operation found at said of necessity/operation finding means; second means for storing a plurality of invalidation execute information found at said necessity of operation finding means corresponding to said access requests stored in said first storing means; and for means/receiving a new read access request and the access request stored in said first storing means and outputting one access request from - received/requests to said necessity / operation finding means in accordance with a predetermined priority order; said tag information storing and updating means effecting an invalidation operation and/or transmission operation of the invalidation information on said central processor in response to information stored in said necessity/operation finding means and said second storing means.
Claim 3
Dependent Claim
104 words
A tag control circuit according to claim 1, wherein said tag information storing and updating means includes a plurality of register groups, the number of which is equal to that of data blocks in said buffer storage, of said necessity/operation finding means includes a plurality of circuits for determining the necessity of operation, the number of which is equal to that of said register groups in said tag information storing an updating circuit, and said second storing means includes a plurality of registers, the number of which is equal to that of said register groups in said tag information storing andupdating circuit. 1 or
Claim 4
Dependent Claim
78 words
A tag control circuit according to claim1 or 2, wherein said first storing means includes a plurality of steps of registers connected in series and in parallel with each other, and said second storing means includes a plurality of steps of registers connected in series and in parallel with each other, a number of steps of which is the same as that of said first storing means, said first and second storing means being operated at synchronous timings.
Claim 5
Dependent Claim
36 words
A tag control circuit according to claim 3, wherein the number of said steps of registers of said first storing means is defined by the number of read access requests output consecutively in a predetermined period.
Claim 6
Dependent Claim
104 words
A tag control circuit according to claim 4, wherein said tag information storing andupdating means includes a plurality of register groups, the number of which is equal to that of data blocks in said buffer storage, of said necessity/operation finding means includes a plurality of circuits for determining the necessity of operation, the number of which is equal to that of said register groups in said tag information storing and updating circuit, and said second storing means includes a plurality of registers, the number of which is equal to that of said register groups in said tag information storing and updating circuit. any preceding
Claim 7
Dependent Claim
51 words
A tag control circuit according to / claim, wherein said tag control circuit further includes third means for storing only store access requests to said main storage before supplying them to said necessity of operation finding means, an output of which is connected to said access request receiving and outputting means.
Claim 8
Dependent Claim
51 words
A tag control circuit according to claim 6, wherein said access request receiving and outputting means outputs one access request defined by the following priority order: a new read access request, an access request stored in said first storing means, and a store access request stored in said third storing means.
Claim 9
Dependent Claim
19 words
A tag control circuit according to/claim, wherein said-tag control circuit further includes means for adding redundancy to error discrimination.
Claim 10
Dependent Claim
48 words
A tag control circuit according to claim 8, wherein said redundancy adding means includes a counter for counting an error or fault of said buffer storage, and wherein said redundancy adding means outputs an invalidation signal when the counted value exceeds a predetermined value during a predetermined period.
Claim 11
Dependent Claim
27 words
A tag control circuit according to claim -8 or 9, wherein said redundancy adding means discriminates error in each data block of said buffer storage with redundancy.
References Cited (Backward Citations)
No citation records indexed.
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