EP0165822A2
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EP
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Memory access control system
Assignee: Fujitsu Ltd
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Filing: 1985-06-21
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Granted: —
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Expires: 2005-06-21
Abstract
Abstract A memory access control system including at least one main memory (10') having a plurality of memory banks (12a o . 12b o , ..... 12a n , 12b n ) divided into two groups (12a o , 12a 1 , ... 12a n ), (12b o , 12b,, ... 12b o ) thus enabling parallel processing for data; a command/address bus line, a write data bus line (17), and a read data bus line (18); and a device for simultaneously activating one request for access to the memory bank belonging to one group and another request for access to the memory bank belonging to the other group.
Inventors
- 👤 Takashi Dai 2 Saginuma Gurin Hiru 206 Chiba
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 17:05
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F12/00; G06F12/02; G06F12/04; G06F12/06; G06F12/0607; G06F13/1605; G06F13/1647
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
78 words
A memory access control system comprising: at least one main memory having a plurality of memory banks divided into two groups, enabling parallel processing for data, a command/address bus line, a write data bus line, and a read data bus line, and means for simultaneously activating one access request for one of said plurality of memory banks belonging to one group and another access request for one of said plurality of memory banks belonging to the other group.
Claim 2
Dependent Claim
78 words
A memory access control system comprising: at least one main memory having a plurality of memory banks divided into two groups, enabling parallel processing for data, a command/address bus line, a write data bus line, and a read data bus line, and means for simultaneously activating one access request for one of said plurality of memory banks belonging to one group and another access request for one of said plurality of memory banks belonging to the other group.
Claim 3
Dependent Claim
34 words
A memory access control system as claimed in claim 1, wherein said two groups of said plurality of memory banks are constituted by memory banks having even numbers and memory banks having odd numbers.
Claim 4
Dependent Claim
59 words
A memory access control system as claimed in or 2, claim 1,/wherein said activating means comprises a command/address register for sending two word commands and for designating an address of a selected memory bank, a decoder for activating a designated memory bank, a write data register for transferring write data, and a read data register for transferring read data.
Claim 5
Dependent Claim
58 words
A memory access control system as claimed in 2 or 3, claim l,J wherein said activating means further comprises a control pipeline register for controlling an output timing of read data, a write data pipeline register for controlling a write timing of partial store data, and two selectors for merging said partial store data with said write data.
Claim 6
Dependent Claim
44 words
A memory access control system as claimed in any claim, preceding/ wherein said activating means further comprises bank registers corresponding to said plurality of memory banks, each of said bank registers having an address register, a write data register, and a read data register.
Claim 7
Dependent Claim
86 words
A memory access control system as claimed in claim 2, or any one of claims 3 to 5 when appended to claim 2, wherein a said even number memory bank and an adjoining odd number memory bank are simultaneously accessed by said address register based on said two word command, and said even number memory bank stores data at the same timing of said access, but said odd number memory bank stores data after a delay of one cycle compared with said even number memory bank.
Claim 8
Dependent Claim
98 words
A memory access control system as claimed in claim 2, or any one of claims 3 to 6 when appended to claim 2, wherein a said even number memory bank and an adjoining odd number memory bank are simultaneously accessed by said address register based on said two word command, and said even number memory bank reads out data at a timing of specific cycles after said access, but said odd number memory bank reads out data after a delay of one cycle compared with said even number memory bank under the control of said control pipeline register.
Claim 9
Dependent Claim
66 words
A memory access control system as claimed in claim 2, or any one of claims 3 to 7 when appended to claim 2, wherein said even number memory bank comprises a counter circuit constituted by flip-flop gates, AND gates, OR gates, and exclusive OR gates for holding contents of an address register and a write data register provided to an input portion of said memory bank.
Claim 10
Dependent Claim
82 words
A memory access control system as claimed in claim 2, or any one of claims 3 to 8 when appended to claim 2, wherein a said odd number memory bank comprises a counter circuit constituted by flip-flop gates, AND gates, OR gates, and exclusive OR gates for holding contents of an address register and a write data register provided to an input portion of said memory bank and for delaying write and read timing to said memory bank by only one cycle.
Claim 11
Dependent Claim
39 words
A memory access control system as claimed in claim 3, or any one of claims 4 to 9 when appended to claim 3, wherein said two word command comprises a sixteen bytes command constituted by two eight bytes commands.
Claim 12
Dependent Claim
35 words
A memory access control system as claimed in any preceding claim, further comprising a memory control unit for controlling said command/address register, said write data register and said read data register in said main memory.
Claim 13
Dependent Claim
29 words
A memory access control system as claimed in claim 11, wherein said memory control unit comprises a plurality of input ports for central processing units and channel processing units.
Claim 14
Dependent Claim
40 words
A memory access control system as claimed in claim 12, wherein each of said plurality of input ports comprises at least two input ports, said two input ports being an upper eight bytes port and a lower eight bytes port
Claim 15
Dependent Claim
30 words
A memory access control system as claimed in any preceding claim, wherein said write data bus line and read data bus line are used simultaneously for parallel processing of data.
References Cited (Backward Citations)
No citation records indexed.
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