Buried-gate structure-type semiconductor switching device

Claim 1

In a semiconductor switching device having a controlling layer therewithin for controlling a switchable device current, the improvement wherein at least one longitudinal direction of the controlling layer is formed substantially in parallel with at least one of crystal axes indicated by <2nn> on a crystal plane indicated by {n11} in Miller indices, where n denotes 0, 1, 2, 3, ..., on condition that inner product of a crystal axis vector and a crystal plane vector is zero.

Claim 12

A method of manufacturing a gate turn-off thyristor, which comprises the following steps of: (a) preparing an N-type semiconductor wafer WA having an exposed crystal plane indicated by {n11} in Miller indices; (b) diffusing impurity atoms on both the exposed surfaces of the prepared semiconductor wafer to form a first semiconductor layer P 1 and a second semiconductor layer P 2 in accordance with diffusion method; (c) forming a pattern mask on the second semiconductor layer P 2 to form a buried gate P 2 ++ and current channels CH in accordance with photo engraving process in such a way that at least one longitudinal direction of current channels CH formed between the buried gate layers P 2 ++ is arranged substantially in parallel with at least one of crystal axes indicated by <2nn> on the crystal plane indicated by {n11} on condition that inner product of a-specific crystal plane vector and a specific crystal axis vector is zero; (d) diffusing impurity atoms on the second semiconductor layer P 2 through the formed pattern mask to form the buried gate layers P 2 " and the current channels CH; (e) forming a third semiconductor layer P 2 - on the second semiconductor layer P 2 and the buried gate layers p 2 ++ in accordance with epitaxial growth method; (f) forming a pattern mask on the third semiconductor layer P 2 - to form a fourth semiconductor layer N 2 ; (g) diffusing impurity atoms on the third semiconductor layer P 2 - to form a fourth semiconductor layer N 2 ; and (h) forming an anode electrode A on the first semiconductor layer P 3 , a gate electrode G on the third semiconductor layer P 2 - and a cathode electrode K on the fourth semiconductor layer N 2 .

Claim 13

A method of manufacturing a gate turn-off thyristor, which comprises the following steps of: (a) preparing an N-type semiconductor wafer WA having an exposed crystal plane indicated by {n11} in Miller indices; (b) diffusing impurity atoms on both the exposed surfaces of the prepared semiconductor wafer to form a first semiconductor layer P 1 and a second semiconductor layer P 2 in accordance with diffusion method; (c) forming a pattern mask on the second semiconductor layer P 2 to form a buried gate P 2 ++ and current channels CH in accordance with photo engraving process in such a way that at least one longitudinal direction of current channels CH formed between the buried gate layers P 2 ++ is arranged substantially in parallel with at least one of crystal axes indicated by <2nn> on the crystal plane indicated by {n11} on condition that inner product of a-specific crystal plane vector and a specific crystal axis vector is zero; (d) diffusing impurity atoms on the second semiconductor layer P 2 through the formed pattern mask to form the buried gate layers P 2 " and the current channels CH; (e) forming a third semiconductor layer P 2 - on the second semiconductor layer P 2 and the buried gate layers p 2 ++ in accordance with epitaxial growth method; (f) forming a pattern mask on the third semiconductor layer P 2 - to form a fourth semiconductor layer N 2 ; (g) diffusing impurity atoms on the third semiconductor layer P 2 - to form a fourth semiconductor layer N 2 ; and (h) forming an anode electrode A on the first semiconductor layer P 3 , a gate electrode G on the third semiconductor layer P 2 - and a cathode electrode K on the fourth semiconductor layer N 2 .