EP0164972A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Shared memory multiprocessor system
Assignee: AT&T Inc
•
Filing: 1985-05-31
•
Granted: —
•
Expires: 2005-05-31
Abstract
Abstract In a system comprising a plurality of processors (1, 2, 3) interconnected by an inter- processor communication controller (ICC) (4), information is transferred from one processor to another via the ICC. Commands from an originating processor are entered in the ICC and responses from the ICC are returned to either the originating or the terminating processor. The response from the ICC includes the address of the first buffer location and the length of the buffer for holding data to be received from an originating processor or to be transferrred to a terminating processor. The data buffers (9, 10, 11) are read by a terminating processor by issuing commands to the ICC.
Inventors
- 👤 Hou Shing Frank Shu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 10:27
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F13/00; G06F13/14; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
86 words
A system for providing communication between any two of a plurality of processors, said system CHARACTERIZED BY an interprocessor communication controller (ICC), an arbitor for determining which of said processors may access ICC at any time, a plurality of transceivers for receiving commands from one of said processors and for sending said commands to an address buffer; and for receiving responses from a data buffer and for sending said processors, and interrupt signal generating means to permit said ICC to interrupt selectively each of said processors.
Claim 2
Independent Claim
86 words
A system for providing communication between any two of a plurality of processors, said system CHARACTERIZED BY an interprocessor communication controller (ICC), an arbitor for determining which of said processors may access ICC at any time, a plurality of transceivers for receiving commands from one of said processors and for sending said commands to an address buffer; and for receiving responses from a data buffer and for sending said processors, and interrupt signal generating means to permit said ICC to interrupt selectively each of said processors.
Claim 3
Dependent Claim
54 words
The system of claim 1 wherein said ICC is CHARACTERIZED BY a random access memory (RAM) for receiving and storing an application program from any one of said processors, a read only memory (ROM) for storing a control program, and a central processing unit (CPU) for executing said control program and said application program.
Claim 4
Dependent Claim
58 words
The system of claim 2 wherein said RAM is CHARACTERIZED BY a free command descriptor buffer pool, a free response descriptor buffer pool, a free data buffer pool, a plurality of command descriptor queues, a plurality of response descriptor queues, a plurality of data queues, a plurality of command queue descriptors, and a plurality of response queue descriptors.
Claim 5
Dependent Claim
91 words
The system of claim 3 wherein said free command descriptor buffer pool is CHARACTERIZED BY the number of free command descriptors in said free command descriptor buffer pool, a pointer for indicating the address of the first free command descriptor in said free command descriptor buffer pool, and a pointer for indicating the address of the last command descriptor in said free command descriptor buffer pool, said free command descriptors forming a linked list wherein each of said free command descriptors points to the next one of said free command descriptors.
Claim 6
Dependent Claim
91 words
The system of claim 3 wherein said free response descriptor buffer pool is CHARACTERIZED BY the number of free response descriptors in said free response descriptor buffer pool, a pointer for indicating the address of the first free response descriptor in said free response descriptor buffer pool, and a pointer for indicating the address of the last response descriptor in said free response descriptor buffer pool, said free response descriptors forming a linked list wherein each of said free response descriptors points to the next one of said free response descriptors.
Claim 7
Dependent Claim
92 words
The system of claim 3 wherein said free data descriptor buffer pool is CHARACTERIZED BY the number of free data descriptors in said free data descriptor buffer pool, a pointer for indicating the address of the first free data descriptor in said free data descriptor buffer pool, and a pointer for indicating the address of the last free data descriptor in said free data descriptor buffer pool, said free data descriptors forming a linked list wherein each of said free data descriptors points to the next one of said free data descriptors.
Claim 8
Dependent Claim
58 words
The system of claim 3 wherein each of said command descriptor queues is CHARACTERIZED BY a plurality of linked command descriptors where each is for pointing to the next command descriptor in the command descriptor queue, and each of the command descriptors comprising plurality of fields for holding the name of the command and information about the command.
Claim 9
Dependent Claim
58 words
The system of claim 3 wherein each of said response descriptor is CHARACTERIZED BY a plurality of linked response descriptors for pointing to the next one of said response descriptors in said response descriptor queue, and each of said response descriptors comprising a plurality of fields for holding the name of the response and information about the response.
Claim 10
Dependent Claim
72 words
The system of claim 3 wherein each of said command queue descriptors is CHARACTERIZED BY the number of commands in said command descriptor queue is controlled by said ICC, a pointer controlled_by the ICC for indicating the address of the first command descriptor in said command descriptor queue, and a second pointer controlled by one of the processors for indicating the address of the last command descriptor in said command descriptor queue.
Claim 11
Dependent Claim
74 words
The system of claim 3 wherein each of said response queue descriptors is CHARACTERIZED IN THAT -the number of responses in said response descriptor queue is controlled by said ICC, a pointer indicating the address of the first response descriptor in said response descriptor queue is controlled by one of said- processors, and a second pointer indicating the address of the last response descriptor in said response descriptor queue is controlled by said ICC.
Claim 12
Independent Claim
127 words
A method of transferring information between any two processors in a system comprising a plurality of processors CHARACTERIZED BY initiating a request from a first one of said processors to an interprocessor communication controller ( I CC) to open a communication channel with a second one of said processors, responding to said request by said ICC when said second processor is available, requesting said ICC by said first processor to determine if said ICC has the required space for receiving and temporarily holding information from said first processor, responding by said ICC to said first processor when said required space becomes available, sending said information from said first processor to said ICC, interrupting said second processor by said ICC, and reading said information by said second processor.
Claim 13
Independent Claim
127 words
A method of transferring information between any two processors in a system comprising a plurality of processors CHARACTERIZED BY initiating a request from a first one of said processors to an interprocessor communication controller ( I CC) to open a communication channel with a second one of said processors, responding to said request by said ICC when said second processor is available, requesting said ICC by said first processor to determine if said ICC has the required space for receiving and temporarily holding information from said first processor, responding by said ICC to said first processor when said required space becomes available, sending said information from said first processor to said ICC, interrupting said second processor by said ICC, and reading said information by said second processor.
Claim 14
Dependent Claim
96 words
The method of claim 11 further comprising the steps of looking up a free command descriptor buffer pool in said ICC by said first processor, obtaining a free command descriptor from said free command descriptor buffer pool, entering said command in said free command descriptor and placing said command descriptor at the end of a command descriptor queue associated with said first processor, and changing a second pointer in a command queue descriptor associated with said first processor by entering the address of said command descriptor which was most recently entered in said command descriptor queue.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.