A method of fabricating self-aligned regions in a substrate

Claim 1

A method of fabricating self-aligned regions in a substrate comprising: forming a first mask 'on a first material on said substrate with at least one opening therein; introducing impurities of a first conductivity type into said substrate through said opening in said first mask to form a first well region; applying a second mask layer of a second material to at least fill said opening in said first mask and covering said first mask; removing said second mask layer sufficient to reveal at least a portion of said first mask; selectively removing said first mask with any superimposed second mask layer to form a second mask being the reverse image of said first mask; and introducing impurities of a second conductivity type into said substrate through openings in said second mask to form second well regions aligned with said first well regions.

Claim 2

A method of fabricating self-aligned regions in a substrate comprising: forming a first mask 'on a first material on said substrate with at least one opening therein; introducing impurities of a first conductivity type into said substrate through said opening in said first mask to form a first well region; applying a second mask layer of a second material to at least fill said opening in said first mask and covering said first mask; removing said second mask layer sufficient to reveal at least a portion of said first mask; selectively removing said first mask with any superimposed second mask layer to form a second mask being the reverse image of said first mask; and introducing impurities of a second conductivity type into said substrate through openings in said second mask to form second well regions aligned with said first well regions.

Claim 3

A method of fabricating self-aligned regions in a substrate comprising: forming a first mask of a first material on said substrate with at least one opening therein; introducing impurities of a first conductivity type into said substrate through said opening in said mask to form a first well regions; applying a second mask layer of a second material overfilling said opening in said first mask and covering said first mask; applying a planarization layer of a third material over said second mask layer to provide a substantially planar top surface; removing said planarization layer and second mask layer sufficient to reveal said first mask; selectively removing said first mask to form a second mask, the reverse image of said first mask; and introducing impurities of a second conductivity type into said substrate through openings in said second mask to form second well regions aligned with said first well regions.

Claim 4

A method of fabricating self-aligned regions in a substrate comprising: forming a first mask of a first material on said substrate with at least one opening therein; introducing impurities of a first conductivity type into said substrate through said opening in said mask to form a first well regions; applying a second mask layer of a second material overfilling said opening in said first mask and covering said first mask; applying a planarization layer of a third material over said second mask layer to provide a substantially planar top surface; removing said planarization layer and second mask layer sufficient to reveal said first mask; selectively removing said first mask to form a second mask, the reverse image of said first mask; and introducing impurities of a second conductivity type into said substrate through openings in said second mask to form second well regions aligned with said first well regions.

Claim 10

A method of fabricating self-aligned regions in a substrate comprising: applying a first mask layer of a first material on a substrate; forming a second mask layer of a second material on said first mask layer with at least one opening therein; removing a portion of said first mask layer in said second mask layer opening to form an opening to reveal said substrate; introducing impurities of a first conductivity type into said substrate through said opening in said first and second mask to form a first well region; applying a third mask layer of a third material to at least fill said opening in said first mask; removing said third mask layer until a portion of said second mask is revealed; selectively removing said second mask with any superimposed third layer to reveal said first mask layer; selectively removing said first mask. to form a second mask, the reverse image of said first mask; and introducing impurities of a second conductivity type into said substrate through openings in said second mask to form second well regions aligned with said first well regions.

Claim 11

A method of fabricating self-aligned regions in a substrate comprising: applying a first mask layer of a first material on a substrate; forming a second mask layer of a second material on said first mask layer with at least one opening therein; removing a portion of said first mask layer in said second mask layer opening to form an opening to reveal said substrate; introducing impurities of a first conductivity type into said substrate through said opening in said first and second mask to form a first well region; applying a third mask layer of a third material to at least fill said opening in said first mask; removing said third mask layer until a portion of said second mask is revealed; selectively removing said second mask with any superimposed third layer to reveal said first mask layer; selectively removing said first mask. to form a second mask, the reverse image of said first mask; and introducing impurities of a second conductivity type into said substrate through openings in said second mask to form second well regions aligned with said first well regions.

Claim 13

A method of fabricating self-aligned regions in a substrate comprising: applying a first mask layer of photosensitive resist material; exposing said first mask layer to a pattern to form exposed and unexposed areas in said first layer; selectively removing said exposed areas to form a first mask having at least one opening therein; introducing impurities of a first conductivity type into said substrate through said opening in said mask to form a first well region; exposing said first mask to form only exposed portions; applying a second mask layer of a photosensitive-resist material to at least fill said opening in said first mask and covering said first mask; removing said second mask layer sufficient to reveal at least portions of said first mask; selectively removing said first mask with any superimposed second mask layer to form a second mask being the reverse image of said first mask; and introducing impurities of a second conductivity type into said substrate through openings in said second mask to form second well regions aligned with said first well regions.

Claim 14

A method of fabricating self-aligned regions in a substrate comprising: applying a first mask layer of photosensitive resist material; exposing said first mask layer to a pattern to form exposed and unexposed areas in said first layer; selectively removing said exposed areas to form a first mask having at least one opening therein; introducing impurities of a first conductivity type into said substrate through said opening in said mask to form a first well region; exposing said first mask to form only exposed portions; applying a second mask layer of a photosensitive-resist material to at least fill said opening in said first mask and covering said first mask; removing said second mask layer sufficient to reveal at least portions of said first mask; selectively removing said first mask with any superimposed second mask layer to form a second mask being the reverse image of said first mask; and introducing impurities of a second conductivity type into said substrate through openings in said second mask to form second well regions aligned with said first well regions.

Claim 15

A method for forming complementary insulated gate field effect transistors comprising: forming a first mask layer having a first opening on a substrate of a first conductivity type; introducing second conductivity type impurities opposite said first conductivity type into said substrate through said opening to form simultaneously a second conductivity type well having a higher impurity concentration at the bottom of said well and a guard ring; forming a second mask on said surface, the reverse image of said first mask using said first mask as a template; introducing first conductivity type impurities into said substrate through an opening in said second mask to form simultaneously a first conductivity type well having a-higher impurity concentration at the bottom of said well and a guard ring; forming a gate insulative layer on said substrate; forming first and second-gates on said gate insulative layer over said first and second wells, respectively; introducing second conductivity type impurities into said first well using said first gate as a mask to form shallow source and drain regions; introducing first conductivity type impurities into said second well using said second gate on a mask to form shallow source and drain regions; forming insulative spacers extending lateral from said first and second gates over said source and drain regions; introducing first conductivity type impurities into said second well using said second gate and spacers as a mask to form deep source and drain regions having a greater depth than said shallow source and drain regions; and introducing second conductivity type impurities into said first well using said first gate and spacers as a mask to form deep source and drain regions having a greater depth than said shallow source and drain regions.

Claim 16

A method for forming complementary insulated gate field effect transistors comprising: forming a first mask layer having a first opening on a substrate of a first conductivity type; introducing second conductivity type impurities opposite said first conductivity type into said substrate through said opening to form simultaneously a second conductivity type well having a higher impurity concentration at the bottom of said well and a guard ring; forming a second mask on said surface, the reverse image of said first mask using said first mask as a template; introducing first conductivity type impurities into said substrate through an opening in said second mask to form simultaneously a first conductivity type well having a-higher impurity concentration at the bottom of said well and a guard ring; forming a gate insulative layer on said substrate; forming first and second-gates on said gate insulative layer over said first and second wells, respectively; introducing second conductivity type impurities into said first well using said first gate as a mask to form shallow source and drain regions; introducing first conductivity type impurities into said second well using said second gate on a mask to form shallow source and drain regions; forming insulative spacers extending lateral from said first and second gates over said source and drain regions; introducing first conductivity type impurities into said second well using said second gate and spacers as a mask to form deep source and drain regions having a greater depth than said shallow source and drain regions; and introducing second conductivity type impurities into said first well using said first gate and spacers as a mask to form deep source and drain regions having a greater depth than said shallow source and drain regions.

Claim 20

A method for forming complementary insulated gate field effect transistors comprising: forming at least one insulative insert in a substrate of a first conductivity type to form at least a first and second mesas in said surface; forming a first mask layer having an opening over said second mesa and a portion of said insulative insert; introducing second conductivity type impurities opposite said first conductivity type into said substrate through said opening to form a second conductivity well i-n said second mesa and under a portion of said insert and having a higher impurity concentration at the bottom of said well; forming a second mask on said surface, the inverse image of said first mask using said first mask as a template; introducing first conductivity type impurities into said substrate through an opening in said second mask to form a first conductivity type-well in said first mesa and under the remainder of said insert and having a higher impurity concentration at the bottom of said well; removing said second mask; forming a gate insulative layer on said mesas; forming a first and second gate on said insulative layer on said first and second mesas, respectively; introducing first conductivity type impurities into said second mesa to form source and drain regions; and introducing first conductivity type impurities into said second mesa to form source and drain regions.

Claim 21

A method for forming complementary insulated gate field effect transistors comprising: forming at least one insulative insert in a substrate of a first conductivity type to form at least a first and second mesas in said surface; forming a first mask layer having an opening over said second mesa and a portion of said insulative insert; introducing second conductivity type impurities opposite said first conductivity type into said substrate through said opening to form a second conductivity well i-n said second mesa and under a portion of said insert and having a higher impurity concentration at the bottom of said well; forming a second mask on said surface, the inverse image of said first mask using said first mask as a template; introducing first conductivity type impurities into said substrate through an opening in said second mask to form a first conductivity type-well in said first mesa and under the remainder of said insert and having a higher impurity concentration at the bottom of said well; removing said second mask; forming a gate insulative layer on said mesas; forming a first and second gate on said insulative layer on said first and second mesas, respectively; introducing first conductivity type impurities into said second mesa to form source and drain regions; and introducing first conductivity type impurities into said second mesa to form source and drain regions.