EP0164138A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data processing system with a plurality of input/output buses
Assignee: EMC Corp
•
Filing: 1981-02-11
•
Granted: —
•
Expires: 2001-02-11
Abstract
Abstract A CPU (10) communicates with various devices on a system bus (11) and communicates with two further groups of devices by way of interfaces (14) and (14A) and corresponding buses (15B) and (15A) whose timing and control characteristics are different from each other and from those of the system bus (11). The interface (14) polls the device which may be on its bus (15B) and keeps a record of the devices actually present. When access to a device is required, the interface (14) provides access via its bus (15B) if the device is recorded as present on that bus. Otherwise it provides a signal to the interface (14a) to enable access via the corresponding bus (15A).
Inventors
- 👤 David H. Bernstein
- 👤 Richard A. Carberry
- 👤 Michael B. Druke
- 👤 Ronald I. Gusowski
- 👤 Edward M. Buckley
- 👤 Roger W. March
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 01:16
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/667; G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/22; G06F13/36; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/268
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
197 words
A data processing system having a central processor unit (10) and a system bus (11) for providing communication with one or more memory units (12), first and second interfaces (14A and 14) providing communication between the system bus (11) and a first and second input/output buses (15A, 15B) in further communication with first and second groups respectively of external units and wherein at least one interface stores a table of external devices addressable thereby characterised in that the second interface (14) includes a control signal connection to the first interface (14A), means (68-71) for polling the devices on the second input/output bus (15B) to identify each of the external devices of the second group which are currently in communication with the second input/output bus (15), means (73) for storing information which indicates the thus identified external devices of the second group, and means (74) responsive to the stored information for controlling the operation of the second interface (14) to provide access to the identified external devices via the second input/output bus (15B) and to provide access to external devices on the first input/output bus (15A) when such devices are not identified as on the second bus (15B).
Claim 2
Dependent Claim
197 words
A data processing system having a central processor unit (10) and a system bus (11) for providing communication with one or more memory units (12), first and second interfaces (14A and 14) providing communication between the system bus (11) and a first and second input/output buses (15A, 15B) in further communication with first and second groups respectively of external units and wherein at least one interface stores a table of external devices addressable thereby characterised in that the second interface (14) includes a control signal connection to the first interface (14A), means (68-71) for polling the devices on the second input/output bus (15B) to identify each of the external devices of the second group which are currently in communication with the second input/output bus (15), means (73) for storing information which indicates the thus identified external devices of the second group, and means (74) responsive to the stored information for controlling the operation of the second interface (14) to provide access to the identified external devices via the second input/output bus (15B) and to provide access to external devices on the first input/output bus (15A) when such devices are not identified as on the second bus (15B).
Claim 3
Dependent Claim
114 words
A data processing system in accordance with claim 1, characterised in that the identifying means includes a poll register means (68, 69) for supplying coded information with respect to all external devices incuded in the second group, means responsive to information (IOCLK) generated in response to the coded information by each external device of the second group which is present on the second input/output bus (15B) for producing a signal (p NEXIST) which indicates that the external device is so present on the second input/output bus (15B), and in that the storing means (73) is responsive to the last-named signal and to the coded information for storing information indicating the presence of external devices.
Claim 4
Dependent Claim
71 words
A data processing system in accordance with claim 2, characterised in that the storing means (73) provides a sensing signal (µ NSNSR) identifying the presence of an external device on the second input/output bus (15B) and further including bus control means (75) responsive to the sensing signal for providing selected control signals to permit access by the system bus means to the second input/output bus (15B) via the second interface (14).
References Cited (Backward Citations)
US4000485A
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.