EP0164095A2
Expired / Lapsed
EP
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Vertical bidirectional stacked power fet
Assignee: Eaton Corp
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Filing: 1985-06-04
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Granted: —
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Expires: 2005-06-04
Abstract
Abstract A vertical bidirectional multi-channel stacked power FET (40) has a plurality of alternating conductivity type layers extending laterally horizontally and stack vertically between top and bottom major surfaces (44,46). The stack (48) includes a plurality of channel-containing regions (49-54) interleaved with a plurality of source regions (55-61). A notch (70) extends downwardly through the lowermost channel-containing region of the stack and includes an insulated gate electrode (68) for inverting the conductivity type of the channel-containing regions to induce conduction channels (49a-54a) between the source regions and enable bidirectional field effect current conduction between the top and bottom surfaces. OFF state voltage is dropped in each direction serially across the junctions between the layers such that depletion region spreading from a plurality of junctions must be vertically coupled before OFF state breakdown.
Inventors
- 👤 James Anthony Benjamin
- 👤 Robert Walter Lade
- 👤 Herman Peter Schutten
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 17:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/668; H10D10/00; H10D10/40; H10D30/01; H10D30/021; H10D30/025; H10D30/791; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/016; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
86 words
A vertical bidirectional multi-channel stacked power FET comprising a semiconductor body having top and bottom major surfaces and a plurality of alternating conductivity type layers extending laterally horizontally and stacked vertically between said top and said bottom surfaces, said stack comprising a plurality of channel-containing regions interleaved with a plurality of source regions, and gate means for inverting the conductivity type of said channel-containing regions to induce conduction channels between said source regions and enable bidirectional field effect current conduction between said top and bottom surfaces.
Claim 2
Dependent Claim
86 words
A vertical bidirectional multi-channel stacked power FET comprising a semiconductor body having top and bottom major surfaces and a plurality of alternating conductivity type layers extending laterally horizontally and stacked vertically between said top and said bottom surfaces, said stack comprising a plurality of channel-containing regions interleaved with a plurality of source regions, and gate means for inverting the conductivity type of said channel-containing regions to induce conduction channels between said source regions and enable bidirectional field effect current conduction between said top and bottom surfaces.
Claim 3
Dependent Claim
78 words
The invention according to claim 1 wherein said layers are stacked between a top source region at said top major surface and a bottom source region at said bottom major surface, and comprising a top main terminal contacting said top source region along said top major surface, and a bottom main terminal contacting said bottom source region along said bottom major surface, the current conduction path between said main terminals traversing serially through said plurality of stacked layers.
Claim 4
Dependent Claim
83 words
The invention according to claim 2 wherein: said source regions are of one conductivity type semiconductor material; said channel-containing regions are of opposite conductivity type semiconductor material; and said gate means comprises gate electrode means proximate said channel-containing regions for applying an electric field to invert the conductivity thereof to said one conductivity type to enable bidirectional current flow serially through a plurality of conduction channels of said one conductivity type interleaved with said pluralitity of source regions of said one conductivity type.
Claim 5
Dependent Claim
152 words
The invention according to claim 3 comprising: notch means in said semiconductor body extending from said top major surface downwardly into said bottom source region and laterally separating said stacked layers into left and right portions; and wherein: said top main terminal has left and right main electrodes respectively contacting left and right top source regions on left and right sides of said notch means along said top major surface; said gate means comprises a layer of insulation along the inner surface of said notch means; said gate electrode means is disposed in said notch means along said insulation layer; said current path between said main terminals traverses generally vertically through said bottom source region below said notch means and traverses along the left and right sides of said notch means through the left and right stacks including the plurality of conduction channels vertically stacked on each side of said notch means.
Claim 6
Dependent Claim
113 words
The invention according to claim 4 wherein said FET has an OFF state in the absence of said gating electric field, with the set of junctions between the said channel-containing regions and respective contiguous source regions therebelow blocking one direction of current flow, and with the alternate set of junctions between said channel-containing regions and respective contiguous source regions thereabove blocking the opposite direction current flow, OFF state voltage between said main terminals being dropped in each direction across the respective set of junctions in series such that depletion region spreading from a plurality of junctions must be vertically coupled before breakdown, whereby to enhance bidirectional voltage blocking capability in said OFF state.
Claim 7
Dependent Claim
25 words
The invention according to claim 5 comprising dedicated gate reference terminal means connected to said channel-containing regions of said opposite conductivity type in said stack.
Claim 8
Dependent Claim
44 words
The invention according to claim 6 wherein said gate reference terminal means comprises a gate reference layer of semiconductor material of said opposite conductivity type extending across and contacting said layers of said stack, and a reference gate electrode contacting said reference gate layer.
Claim 9
Dependent Claim
57 words
The invention according to claim 7 comprising a gate reference groove notched vertically into said stack, and wherein said reference gate layer of semiconductor material of said opposite conductivity type extends along the inner surface of said gate reference groove to contact said layers of said stack, and said reference gate electrode contacts said reference gate layer.
References Cited (Backward Citations)
No citation records indexed.
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