Isolated bidirectional power fet

Claim 2

Isolated bidirectional power FET structure comprising a horizontal layer of semiconductor material of one conductivity type having a vertical isolation region of opposite conductivity type extending from a top major surface of said layer downwardly therethrough to isolate first and second regions of said one conductivity type on opposite sides of said vertical isolation region of said opposite conductivity type, and gate electrode means proximate said isolation region for applying an electric field to convert a portion of the latter to said one cnductivity type and provide a bidirectional conduction channel between said first and second regions.

Claim 3

The invention according to claim 1 wherein said FET has an OFF state in the absence of said electric field, reverting said channel back to said opposite conductivity type to block current flow between said first and second regions, the junction between said first region and said isolation region blocking current flow in one direction, and the junction between said second region and said isolation region blocking current flow in the opposite direction.

Claim 4

The invention according to claim 2 wherein said gate electrode means extends along said top major surface and is spaced above said isolation region by a dielectric layer.

Claim 5

The invention according to claim 3 wherein said converted conduction channel extends horizontally through said isolation region beneath said top major surface.

Claim 6

The invention according to claim 2 comprising a horizontal sublayer of semiconductor material of said opposite conductivity type below said horizontal layer of semiconductor material of said one conductivity type, and wherein said vertical isolation region of said opposite conductivity type extends downwardly through said first mentioned layer and into said sublayer, said sublayer blocking current flow between said first and second regions around the bottom of said isolation region, the junction between said first region and said sublayer blocking current flow in one direction, and the junction between said second region and said sublayer blocking current flow in the opposite direction.

Claim 7

The invention according to claim 1 comprising first and second main electrodes connected respectively to said first and second regions, and wherein: said main electrodes are connectable in an AC load line; said gate electrode means is connectable to a source of gate potential for biasing said gate electrode to apply said electrid field and induce said conduction channel through said isolation region between said first and second regions during each half cycle of said AC line; such that during the first half cycle of said AC line, current flows from said first main electrode through said first region then through said conduction channel then through said second region to said second main electrode; and such that during the second half cycle of said AC line, current flows from said second main electrode through said second region then through said conduction channel then through said first region to said first main electrode.

Claim 8

Isolated bidirectional power FET structure, comprising: a horizontal layer of semiconductor material of one conductivity type having a top major surface; a vertical isolation region of opposite conductivity type extending from said top major surface of said layer downwardly through said layer to isolate first and second regions of said one conductivity type on opposite sides of said vertical isolation region; first and second main electrodes connected respectively to said first and second regions, and connectable in an AC load line; gate electrode means proximate and electrically isolated from said isolation region and connectable to a source of gate potential for biasing said gate electrode to apply an electric field to convert a portion of said isolation region to said one conductivity type and induce a conduction channel through said isolation region between said first and second regions during each half cycle of the AC line such that there is bidirectional field effect conduction between said first and second regions, with their roles reversed in alternate half cycles, such that current flows in one direction during the first half cycle with said first region acting as a drain and said second region acting as a source, and such that current flows in the opposite direction during the second half cycle with said second region acting as a drain and said first region acting as a source; said FET having an OFF state in the absence of said gate potential to eliminate said conduction channel, current flow in one direction during the first half cycle being blocked by the junction between said vertical isolation region and one of said first and second regions, current flow in the opposite direction during the second half cycle being blocked by the junction between said vertical isolation region and the other of said first and second regions, whereby to provide AC blocking capability.

Claim 9

Isolated bidirectional power FET structure, comprising: a horizontal layer of semiconductor material of one conductivity type having a top major surface; a vertical isolation region of opposite conductivity type extending from said top major surface of said layer downwardly through said layer to isolate first and second regions of said one conductivity type on opposite sides of said vertical isolation region; first and second main electrodes connected respectively to said first and second regions, and connectable in an AC load line; gate electrode means proximate and electrically isolated from said isolation region and connectable to a source of gate potential for biasing said gate electrode to apply an electric field to convert a portion of said isolation region to said one conductivity type and induce a conduction channel through said isolation region between said first and second regions during each half cycle of the AC line such that there is bidirectional field effect conduction between said first and second regions, with their roles reversed in alternate half cycles, such that current flows in one direction during the first half cycle with said first region acting as a drain and said second region acting as a source, and such that current flows in the opposite direction during the second half cycle with said second region acting as a drain and said first region acting as a source; said FET having an OFF state in the absence of said gate potential to eliminate said conduction channel, current flow in one direction during the first half cycle being blocked by the junction between said vertical isolation region and one of said first and second regions, current flow in the opposite direction during the second half cycle being blocked by the junction between said vertical isolation region and the other of said first and second regions, whereby to provide AC blocking capability.

Claim 10

The invention according to claim 7 comprising a horizontal sublayer of semiconductor material of said opposite conductivity type below said horizontal layer of semiconductor material of said one conductivity type, and wherein: said vertical isolation region extends downwardly through said first mentioned layer and into said sublayer; said sublayer blocks current flow between said first and second regions around the bottom of said isolation region, the junction between said first region and said sublayer blocking current flow in one direction, and the junction between said second region and said sublayer blocking current flow in the opposite direction; said gate electrode extends along said top major surface and is spaced above said isolation region; and said conduction channel extends horizontally through said isolation region beneath said top major surface.

Claim 11

The invention according to claim 7 wherein said OFF state is provided by removing said gate potential from said gate electrode and applying opposite polarity gate potential to said gate electrode to prevent attraction of minority carriers in said isolation region, to prevent unwanted inducement of a conduction channel during said OFF state.

Claim 12

Isolated bidirectional power FET structure comprising a horizontal top layer of semiconductor material of one conductivity type formed on a horizontal sublayer of semiconductor material of opposite conductivity type, said top layer and said sublayer each having an implanted region of said opposite conductivity type, said implanted regions being thermally grown vertically toward each other to meet and form a vertical isolation region of said opposite conductivity type separating first and-second regions of said one conductivity type on opposite sides thereof in said top layer, and gate electrode means proximate said isolation region for applying an electric field to convert a portion of the latter to said one conductivity type and provide a bidirectional conduction channel between said first and second regions.

Claim 13

Isolated bidirectional power FET structure comprising a horizontal top layer of semiconductor material of one conductivity type formed on a horizontal sublayer of semiconductor material of opposite conductivity type, said top layer and said sublayer each having an implanted region of said opposite conductivity type, said implanted regions being thermally grown vertically toward each other to meet and form a vertical isolation region of said opposite conductivity type separating first and-second regions of said one conductivity type on opposite sides thereof in said top layer, and gate electrode means proximate said isolation region for applying an electric field to convert a portion of the latter to said one conductivity type and provide a bidirectional conduction channel between said first and second regions.

Claim 14

The invention according to claim 10 wherein said implanted region in said sublayer is formed from a top surface thereof, and wherein said implanted region in said top layer is formed from a top surface thereof, said implanted regions being thermally grown to spread vertically through said top layer such that said vertical isolation region of said opposite conductivity type extends from said top surface of said top layer downwardly through said top layer and into said sublayer.