EP0163830A2
Expired / Lapsed
EP
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Multi-layer integrated circuit substrates and method of manufacture
Assignee: International Business Machines Corp
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Filing: 1985-03-22
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Granted: —
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Expires: 2005-03-22
Abstract
Abstract A thin film composite structure consists of at least two layers (M1. M2) of electrical wiring (11, 15) composed of a metal such as copper separated from each other for the most part by an intervening layer of an insulating material such as polyimide. A layer (12, 14) of a composite of an adhesion metal and a conductive metal (Cr-Cu "blend") is interposed between the copper wiring (11, 15) and the insulating material (13) as well as between the copper wiring where they join in regions (16) where the dielectric has been opened to form vias and other electrical junction points between the layers. The preferred composition of the "blend" is in the range from 5-95 atomic percent Cr and 95-5 atomic percent Cu although other metals can be combined with each. The purpose of the thin "blend" film is to enhance the adhesion of the layers while not increasing the resistance of the contacts between the upper and lower conducting layers, at the vias and other electrical junction points.
Inventors
- 👤 Sue Thu-Er Lee
- 👤 Sheree Hsiao-Ru Wen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 17:26
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H05; H05K; H05K3/00; H05K3/38; H05K3/388; H10W70/01; H10W70/05; H10W70/611; H10W70/62; H10W70/66; H05K1/00; H05K1/02; H05K1/03; H05K1/0313; H05K1/032; H05K1/0346; H05K3/46; H05K3/4644; H05K3/467
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
94 words
An integrated circuit assembly comprising a buffer layer (12) interposed between a first conducting layer (11) and dielectric layer(13), characterised in that said buffer layer (12) is contiguous with and directly contacts one surface of the dielectric layer (13), in that said buffer layer (12) comprises a first metal exhibiting a strong adhesion to the dielectric layer (13) and a second metal having a relatively high electrical conductivity and in that the second metal is distributed throughout the buffer layer to provide electrical continuity with high conductivity between the opposed faces of that layer.
Claim 2
Dependent Claim
94 words
An integrated circuit assembly comprising a buffer layer (12) interposed between a first conducting layer (11) and dielectric layer(13), characterised in that said buffer layer (12) is contiguous with and directly contacts one surface of the dielectric layer (13), in that said buffer layer (12) comprises a first metal exhibiting a strong adhesion to the dielectric layer (13) and a second metal having a relatively high electrical conductivity and in that the second metal is distributed throughout the buffer layer to provide electrical continuity with high conductivity between the opposed faces of that layer.
Claim 3
Dependent Claim
38 words
An assembly as claimed in claim 1, further characterised in that a second buffer layer, as aforesaid, directly contacts the other surface of the dielectric layer and is interposed between a second conducting layer and the dielectric layer.
Claim 4
Dependent Claim
45 words
An assembly as claimed in claim 2, further characterised in that the first and second conductors are electrically connected by a portion of the second buffer layer which lines a via hole in the dielectric layer and extends therethrough to join the first buffer layer.
Claim 5
Dependent Claim
30 words
An assembly as claimed in claim 1, 2 or 3, further characterised in that the first metal comprises chromium, titanium, manganese, vanadium, niobium, molybdenum, hafnium, tungsten, tantalum, nickel, or aluminium.
Claim 6
Dependent Claim
23 words
An assembly as claimed in claim 1, 2, 3 or 4, further characterised in that the second metal comprises copper, gold or silver.
Claim 7
Dependent Claim
28 words
An assembly as claimed in any one of claims 1 to 5, further characterised in that the dielectric layer comprises a polymer, a ceramic or a glass material.
Claim 8
Dependent Claim
56 words
An assembly as claimed in any one of claims 1, 2 or 3, further characterised in that the first metal is chromium and is present in the buffer layer in the proportion 5 to 95 atomic percentage and in that the second metal is copper and is present in the proportion 95 to 5 atomic percentage.
Claim 9
Dependent Claim
112 words
A process for making an integrated circuit assembly comprising a buffer layer interposed between a first conducting layer and a dielectric layer, said process comprising forming said first conducting layer on a planar support; forming a buffer layer over said conducting layer by simultaneously depositing thereon a first metal exhibiting a strong adhesion to the material of the dielectric layer and a second metal exhibiting a relatively high electrical conductivity, said co-deposition being carried out so that the second metal is distributed throughout the buffer layer to provide electrical continuity with high conductivity between the opposed faces of that layer; and applying a layer of the dielectric material over the buffer layer.
Claim 10
Dependent Claim
112 words
A process for making an integrated circuit assembly comprising a buffer layer interposed between a first conducting layer and a dielectric layer, said process comprising forming said first conducting layer on a planar support; forming a buffer layer over said conducting layer by simultaneously depositing thereon a first metal exhibiting a strong adhesion to the material of the dielectric layer and a second metal exhibiting a relatively high electrical conductivity, said co-deposition being carried out so that the second metal is distributed throughout the buffer layer to provide electrical continuity with high conductivity between the opposed faces of that layer; and applying a layer of the dielectric material over the buffer layer.
Claim 11
Dependent Claim
115 words
A process for making an integrated circuit assembly comprising a buffer layer interposed between a dielectric layer and a conducting layer, said process comprising providing a dielectric layer; forming a buffer layer over said dielectric layer by simultaneously depositing thereon a first metal exhibiting a strong adhesion to the material of the dielectric layer and a second metal exhibiting a relatively high electrical conductivity, said co-deposition being carried out so that the second metal is distributed throughout the buffer layer to provide electrical continuity with high conductivity between the opposed faces of that layer; and applying a layer of the dielectric material over the buffer layer and forming a conducting layer on the buffer layer.
Claim 12
Dependent Claim
115 words
A process for making an integrated circuit assembly comprising a buffer layer interposed between a dielectric layer and a conducting layer, said process comprising providing a dielectric layer; forming a buffer layer over said dielectric layer by simultaneously depositing thereon a first metal exhibiting a strong adhesion to the material of the dielectric layer and a second metal exhibiting a relatively high electrical conductivity, said co-deposition being carried out so that the second metal is distributed throughout the buffer layer to provide electrical continuity with high conductivity between the opposed faces of that layer; and applying a layer of the dielectric material over the buffer layer and forming a conducting layer on the buffer layer.
Claim 13
Dependent Claim
174 words
A process for making a multilayer integrated circuit assembly, said process comprising forming said first conducting layer on a planar support; forming a buffer layer over said conducting layer by simultaneously depositing thereon a first metal exhibiting a strong adhesion to the material of the dielectric layer and a second metal exhibiting a relatively high electrical conductivity, said co-deposition being carried out so that the second metal is distributed throughout the buffer layer to provide electrical continuity with high conductivity between the opposed faces of that layer; applying a layer of the dielectric material over the buffer layer; forming a second buffer layer over said dielectric layer by simultaneously depositing thereon a first metal exhibiting a strong adhesion to the material of the dielectric layer and a second metal exhibiting a relatively high electrical conductivity, said co-deposition being carried out so that the second metal is distributed throughout the buffer layer to provide electrical continuity with high conductivity between the opposed faces of that layer; and forming a conducting layer on the buffer layer.
Claim 14
Dependent Claim
174 words
A process for making a multilayer integrated circuit assembly, said process comprising forming said first conducting layer on a planar support; forming a buffer layer over said conducting layer by simultaneously depositing thereon a first metal exhibiting a strong adhesion to the material of the dielectric layer and a second metal exhibiting a relatively high electrical conductivity, said co-deposition being carried out so that the second metal is distributed throughout the buffer layer to provide electrical continuity with high conductivity between the opposed faces of that layer; applying a layer of the dielectric material over the buffer layer; forming a second buffer layer over said dielectric layer by simultaneously depositing thereon a first metal exhibiting a strong adhesion to the material of the dielectric layer and a second metal exhibiting a relatively high electrical conductivity, said co-deposition being carried out so that the second metal is distributed throughout the buffer layer to provide electrical continuity with high conductivity between the opposed faces of that layer; and forming a conducting layer on the buffer layer.
Claim 15
Dependent Claim
57 words
A process as claimed in claim 10, further comprising forming a via hole through the dielectric layer to expose the first buffer layer therethrough before forming the second buffer layer, and thereafter forming the second buffer layer to include a portion lining the via hole and electrically joined to the exposed region of the first buffer layer.
References Cited (Backward Citations)
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