Instruction prefetch system for conditional branch instruction for central processor unit

Claim 2

A fetch unit for use in a processor in a digital data processing system for fetching program instructions and operands from a_memory, the memory including a plurality of addressable storage locations for storing program instructions from a first series of program instructions in a first series of successive storage locations, the instructions including a conditional branch instruction which enables the fetch unit to fetch from the memory program instructions from a second series of program instructions stored in a second series of storage locations in response to the occurrence of a predetermined condition in said processor, said fetch unit comprising: A. operand retrieval means for initiating the retrieval of operands from the memory; B. instruction retrieval means for initiating the retrieval of instructions from the memory; and C. control means connected to said operand retrieval means and said instruction retrieval means for controlling the operation thereof, said control means being responsive to the receipt of a conditional branch instruction to enable said operand retrieval means to initiate a retrieval from the memory of an instruction from the second series of program instructions in response to the processor indicating the occurrence of the predetermined condition.

Claim 3

A fetch unit as defined in claim 1 wherein the operand retrieval means and the instruction retrieval means both include means for calculating the address in memory of a respective operand or instruction and said control means includes means for receiving a signal from the processor indicating the presence or absence of the predetermined condition.

Claim 4

A fetch unit as defined in claim 2 further comprising buffer means for storing an instruction comprising an operation code and an operand specifier defining the location in memory of an operand, A. said operand retrieval address calculation means means comprising: (i) means for decoding each operand specifier in the instruction to determine the address in memory of an operand, and (ii) means connected to said decoding means for storing the decoded operand address, E. said control means including means responsive to the conditional branch instruction operation code when said instruction buffer contains a conditional branch instruction for enabling said operand retrieval address calculation means to decode the operand specifier of the conditional branch instruction and initiate the retrieval from the memory of an instruction from the second series of program instructions.

Claim 5

4 . A fetch unit as defined in claim 3 in which the operand specifier of a conditional branch instruction constitutes the displacement in addressable storage locations from the conditional branch instruction to the second series of program instructions, wherein: A. said operand retrieval means further includes a program counter register, B. said control means includes: (i) means for enabling the contents of said program counter register and said conditional branch instruction operand specifier to both be coupled to the operand retrieval means address calculation means, and (ii) means for enabling said operand retrieval means address calculation means to perform an addition and storing the sum in said operand address storage means, and C. said operand retrieval means further including means for using the contents of said operand address storage means to initiate the retrieval of an instruction from said second series of instruction and storing the retrieved instruction in said instruction buffer means.

Claim 6

A fetch unit as defined in clair 4 wherein said instruction retrieval means further includes: A. instruction address storage means for storing the address in memory of the next instruction in the first series of instructions; B. means connected to said instruction address storage means for transmitting a request to the memory to initiate a retrieval of the contents of the storage location identified by the contents of said instruction address storage means, and C. said instruction address calculation means being connected to said instruction address storage means and said retrieval initiating means for incrementing the contents of said instruction address storage means when the contents of said instruction address storage means have been used.

Claim 7

A fetch unit as defined in clair 4 wherein said instruction retrieval means further includes: A. instruction address storage means for storing the address in memory of the next instruction in the first series of instructions; B. means connected to said instruction address storage means for transmitting a request to the memory to initiate a retrieval of the contents of the storage location identified by the contents of said instruction address storage means, and C. said instruction address calculation means being connected to said instruction address storage means and said retrieval initiating means for incrementing the contents of said instruction address storage means when the contents of said instruction address storage means have been used.

Claim 8

A fetch unit as defined in claim 5 further comprising coupling means connected to said operand retrieval means address calculation means and said instruction address storage means, said control means enabling said coupling means to couple the address of the second series of instructions for storage in said instruction address storage means when said instruction buffer stores a conditional branch instruction.

Claim 9

A fetch unit as defined in claim 4 wherein said control means further includes means for enabling the contents of said operand address storage means to be stored in said program counter in response to the predetermined condition in said processor.

Claim 10

A fetch unit as defined in claim 2 further including interface means including: A. means for transmitting address, command and memory control signals to the memory, said command signals including signals for enabling the memory to transfer data signals, including instructions and operands, to said fetch unit, and said memory control signals including an abort signal, the memory not transmitting the contents of the addressed location to the fetch unit in response to the receipt of the abort signal, B. means for receiving data signals from the memory, and C. means responsive to the signal from the processor indicating the absence of the predetermined condition to enable the transmission of said abort signal by said interface means to the memory.

Claim 11

A fetch unit as defined in claim 8 wherein said interface means further includes: A. means for receiving an acknowledgment signal from the memory transmitted by the memory in response to its receipt of the address, command and memory control signals from said interface means, and B. means for receiving a response signal from the memory with the data signals which enables said interface means to receive the data signals.

Claim 12

A central processor unit for connection to a memory unit for forming a digital data processing system, the memory including a plurality of addressable storage locations for storing program instructions in a series of successive storage locations and operands for use in processing the instructions, one of the instructions comprising a conditional branch instruction which enables the central processor unit to process program instructions from a second series of storage locations in response to the occurrence of a predetermined condition in said central processor unit, said central processor unit comprising: A. a buffer for storing instructions that have been retrieved from the memory unit, B. instruction retrieval means for connection to said instruction buffer for retrieving program instructions fro 7 said first set of storage locations for storage in said instruction buffer; C. operand retrieval means for retrieving operands from the memory unit; D. control means connected to said buffer, said instruction retrieval means and said instruction retrieval means for controlling the operation thereof, said control means being responsive to a branch instruction in said buffer for enabling said operand retrieval means to retrieve program instructions from the second set of instruction storage locations for storage in said instruction buffer.

Claim 13

A central processor unit for connection to a memory unit for forming a digital data processing system, the memory including a plurality of addressable storage locations for storing program instructions in a series of successive storage locations and operands for use in processing the instructions, one of the instructions comprising a conditional branch instruction which enables the central processor unit to process program instructions from a second series of storage locations in response to the occurrence of a predetermined condition in said central processor unit, said central processor unit comprising: A. a buffer for storing instructions that have been retrieved from the memory unit, B. instruction retrieval means for connection to said instruction buffer for retrieving program instructions fro 7 said first set of storage locations for storage in said instruction buffer; C. operand retrieval means for retrieving operands from the memory unit; D. control means connected to said buffer, said instruction retrieval means and said instruction retrieval means for controlling the operation thereof, said control means being responsive to a branch instruction in said buffer for enabling said operand retrieval means to retrieve program instructions from the second set of instruction storage locations for storage in said instruction buffer.

Claim 14

A central processor unit as defined in claim 10 further including means for determining in response to the occurrence or absence of the predetermined condition, whether the branch is to be taken, said operand retrieval means further including means for disabling an instruction fetch by said operand retrieval means if said processing means determines that the branch is not to be taken.

Claim 15

A central processor unit as defined in claim 11 wherein said instruction buffer includes a multiple- location storage buffer and control means for eliminating instructions remaining in said storage buffer from said first set of instructions in response to the occurrence of the predetermined condition.

Claim 16

A central processor unit as defined in claim 11 wherein the operand retrieval means and the instruction means both include means for calculating the address in memory of a respective operand or instruction.

Claim 17

A central processor unit as defined in claim 13 wherein: A. an instruction stored in said buffer comprises an operation code and an operand specifier defining the location in memory of an operand, B. said operand retrieval address calculation means comprises: (i) means for decoding each operand specifier in the instruction to determine the address in memory of an operand, and (ii) means connected to said decoding means for storing the decoded operand address, and C. said control means includes means responsive to the conditional branch instruction operation code when said instruction buffer contains a conditional branch instruction for enabling said operand retrieval address calculation means to decode the operand specifier of the conditional branch instruction and initiate the retrieval from the memory of an instruction from the second series of program instructions.

Claim 18

A central processor unit as defined in claim 14 in which the operand specifier of a conditional branch instruction constitutes the displacement in addressable storage locations from the conditional branch instruction to the second series of storage locations, wherein: A. said operand retrieval means further includes a program counter register, B. said control means includes: (i) means for enabling the contents of said program counter and said conditional branch instruction operand specifier to both be coupled to the operand retrieval means address calculation means, and (ii) means for enabling said operand retrieval means address calculation means to perform an addition and storing the sum in said operand address storage means, and C. said operand retrieval means further including means for using the contents of said operand address storage means to initiate the retrieval of an instruction from said second series of storage locations and storing the retrieved instruction in said instruction buffer means.

Claim 19

A central processor unit as defined in claim 15 wherein said instruction retrieval means further includes: A. instruction address storage means for storing the address in memory of the next instruction in the first series of instructions; B. means connected to said instruction address storage means for transmitting a request to the memory to initiate a retrieval of the content of the storage location identified by the contents of said instruction address storage means, and C. said instruction address calculation means being connected to said instruction address storage means and said retrieval initiating means for incrementing the contents of said instruction address storage means when the contents of said instruction address storage means have been used.

Claim 20

A central processor unit as defined in claim 16 further comprising coupling means connected to said operand retrieval means address calculation means and said instruction address storage means, said control means enabling said coupling means to couple the address of the second series of instructions for storage in said instruction address storage means when said instruction buffer stores a conditional branch instruction.

Claim 21

A central processor unit as defined in claim 15 wherein said control means further includes means for enabling the contents of said operand address storage means to be stored in said program counter in response to the predetermined condition in said processor.

Claim 22

A central processor unit as defined in claim 13 further including interface means including: A. means for transmitting address, command and memory control signals to the memory, said command signals including signals for enabling the memory to transfer data signals, including instructions and operands, to said fetch unit, and said memory control signals including an abort signal, the memory not transmitting the contents of the addressed location to the fetch unit in response to the receipt of the abort signal, B. means for receiving data signals from the memory, and C. means responsive to processor detecting the absence of the predetermined condition to enable the transmission of said abort signal by said interface means to the memory.

Claim 23

A central processor unit as defined in claim 19 wherein said interface means further includes: A. means for receiving an acknowledgment signal from he memory transmitted by the memory in response to its receipt of the address, command and memory control signals from said interface means, and B. means for receiving a response signal from the memory with the data signals which enables said interface means to receive the data signals.