EP0162774A2
Expired / Lapsed
EP
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Improvements in integrated circuit chip processing techniques and integrated circuit chip produced thereby
Assignee: Digital Equipment Corp
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Filing: 1985-05-10
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Granted: —
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Expires: 2005-05-10
Abstract
Abstract A method of fabricating an integrated circuit chip including insulated gate field effect transistors, and an integrated circuit chip produced thereby. By a series of complementary self-aligned masking operations, the field oxide is produced from an initial oxide layer to define active device regions in which transistors are formed, and field implants are provided only in the field regions under the field oxide. The transistors are then formed so that the level of the top surface of the the gate electrodes corresponds to the level of the top surface of the field oxide. An insulation layer is applied to the sidewalls of the gate electrodes and conductive material is deposited in the recess defined by the gate electrodes and the field oxide. The level of the top surface of the conductive material corresponds to the level of the top surface of the gate electrodes and field oxide. An insulation layer is thn applied to the chip surface. In another aspect, a recess may beformed in the chip under a photoresist layer such that the photoresist overhangs the resist. A metal film is cold-sputtered, filling the recess and covering the photoresist. The film in the recess is separated from the film covering the recess because of the overhang. A second photoresist layer is applied, then etched to expose a corner of the metal film over the overhang. The metal is etched to expose the underlying photoresist, and the underlying photoresist, and the portion of the second layer over the film in the recess, are removed.
Inventors
- 👤 Andrew L. Wu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 01:00
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/011; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038; H10P; H10P76/00; H10P76/20; H10P76/202; H10P76/40; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/058; H10W20/071; H10W20/081; Y; Y10; Y10S; Y10S148/00; Y10S148/105; Y10S438/00; Y10S438/942; Y10S438/945; Y10S438/975
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
183 words
A method of forming an integrated circuit chip on a substrate of a first conductivity type comprising the steps of: A. depositing an insulation layer and a second layer over the surface of a substrate; B. defining the active device regions and removing the portion of the second layer in the field regions to produce recesses in the second layer in the field regions; C. impregnating the surface of the substrate in the field regions with an implant having the first conductivity type to provide a field implant; D. depositing a masking material in the recesses in the second layer to provide a mask defining the field regions; E. removing the remainder of the second layer and the portion of the insulation layer exposed by the removal of the second layer thereby exposing the surface of the substrate to provide the active device regions, the remaining portion of the insulation layer comprising the field insulation layer; and F. removing the masking material from the field insulation layer; thereby providing a field insulation layer on the substrate and a field implant in the substrate.
Claim 2
Independent Claim
183 words
A method of forming an integrated circuit chip on a substrate of a first conductivity type comprising the steps of: A. depositing an insulation layer and a second layer over the surface of a substrate; B. defining the active device regions and removing the portion of the second layer in the field regions to produce recesses in the second layer in the field regions; C. impregnating the surface of the substrate in the field regions with an implant having the first conductivity type to provide a field implant; D. depositing a masking material in the recesses in the second layer to provide a mask defining the field regions; E. removing the remainder of the second layer and the portion of the insulation layer exposed by the removal of the second layer thereby exposing the surface of the substrate to provide the active device regions, the remaining portion of the insulation layer comprising the field insulation layer; and F. removing the masking material from the field insulation layer; thereby providing a field insulation layer on the substrate and a field implant in the substrate.
Claim 3
Dependent Claim
79 words
A method as defined in claim 1 wherein said defining step comprises the steps of: A. depositing a layer of photoresist over the surface of the second layer, exposing the photoresist layer in a pattern defining the field regions and the active device regions and removing the portions of the photoresist layer in the field regions; B. etching the second layer in the field regions not covered by the photoresist layer to provide the recesses in the second layer.
Claim 4
Dependent Claim
16 words
The method as defined in claim 2 wherein the etching step is a reactive ion etch.
Claim 5
Dependent Claim
176 words
The method as defined in claim 2 wherein the recess step provides a recess in which the photoresist layer overhangs the second layer and the masking material deposition step comprises the steps of: A. cold sputtering a layer of metal over the recess and the surface of the photoresist layer, the metal being deposited in a layer in the recess and covering the top and sidewall of the photoresist, with the metal on the photoresist being separated from the metal layer in the recess; B. covering the surface of the chip with a masking material to a depth sufficient to ensure that there is a depression over the recess; C. etching the layer of masking material so as to expose the portion of the metal layer over the corner of the photoresist layer; D. etching the exposed metal to expose the corner and overhang of the photoresist layer; E. removing the photoresist layer, to thereby remove the masking material and metal layers thereover; and F. removing the masking layer over the metal layer in the recess.
Claim 6
Dependent Claim
27 words
The method as defined in claim 4 wherein the masking material is photoresist so that the photoresist removing step and the masking layer removing step occur together.
Claim 7
Dependent Claim
61 words
The method as defined in claim 1 wherein the second layer is polysilicon and the insulation layer is silicon dioxide and the substrate exposing step comprises the steps of: A. applying a mixture of nitric acid, water and hydrofluoric acid to remove the remainder of the second layer; and B. applying a reactive ion etch to remove the exposed silicon dioxide.
Claim 8
Dependent Claim
230 words
7 . A method of forming a recess in an integrated circuit chip and filling it with a metal comprising the steps of: A. depositing a layer of photoresist over the chip and removing the photoresist in a region in which the recess is to be formed; B. forming a recess in the region of the chip defined by the removed photoresist such that the photoresist overhangs the recess; C. cold sputtering a layer of metal over the recess and the surface of the photoresist layer, the metal being deposited in a layer in the recess and covering the top and sidewall of the photoresist, with the metal on the photoresist being separated from the metal layer in the recess; D. covering the surface of the chip with a masking material to a depth sufficient to ensure that there is a depression over the recess; E. etching the layer of masking material so as to expose the portion of the metal layer over the corner of the photoresist layer defined by the top surface and sidewall thereof; F. etching the exposed metal to expose the top surface and sidewall of the photoresist layer in the area of the corner of the photoresist; G. removing the photoresist layer, to thereby remove the masking material and metal layers thereover; and B. removing the masking layer over the metal layer in the recess.
Claim 9
Dependent Claim
230 words
7 . A method of forming a recess in an integrated circuit chip and filling it with a metal comprising the steps of: A. depositing a layer of photoresist over the chip and removing the photoresist in a region in which the recess is to be formed; B. forming a recess in the region of the chip defined by the removed photoresist such that the photoresist overhangs the recess; C. cold sputtering a layer of metal over the recess and the surface of the photoresist layer, the metal being deposited in a layer in the recess and covering the top and sidewall of the photoresist, with the metal on the photoresist being separated from the metal layer in the recess; D. covering the surface of the chip with a masking material to a depth sufficient to ensure that there is a depression over the recess; E. etching the layer of masking material so as to expose the portion of the metal layer over the corner of the photoresist layer defined by the top surface and sidewall thereof; F. etching the exposed metal to expose the top surface and sidewall of the photoresist layer in the area of the corner of the photoresist; G. removing the photoresist layer, to thereby remove the masking material and metal layers thereover; and B. removing the masking layer over the metal layer in the recess.
Claim 10
Dependent Claim
27 words
The method as defined in claim 7 wherein the masking material is photoresist so that the photoresist removing step and the masking layer removing step occur together.
Claim 11
Independent Claim
118 words
A method of forming an integrated circuit chip on a substrate of a first conductivity type comprising the steps of: A. providing active devices in active device regions defined by recesses in a field insulation layer, the upper surface of the gate electrodes of the active devices being at the level of the upper surface of the field insulation layer; B. providing a sidewall insulation layer on the sidewalls of the gate electrodes, the sidewall insulation layer and the sidewalls of the field insulation layer defining recesses; and C. depositing conductive material in the recesses, the upper surfaces of the conductive material in the recesses being at the level of the upper surface of the field insulation layer.
Claim 12
Independent Claim
118 words
A method of forming an integrated circuit chip on a substrate of a first conductivity type comprising the steps of: A. providing active devices in active device regions defined by recesses in a field insulation layer, the upper surface of the gate electrodes of the active devices being at the level of the upper surface of the field insulation layer; B. providing a sidewall insulation layer on the sidewalls of the gate electrodes, the sidewall insulation layer and the sidewalls of the field insulation layer defining recesses; and C. depositing conductive material in the recesses, the upper surfaces of the conductive material in the recesses being at the level of the upper surface of the field insulation layer.
Claim 13
Dependent Claim
21 words
A method as defined in claim 9 further comprising the steps of covering the chip with a layer of insulation material.
Claim 14
Dependent Claim
15 words
A method as defined in claim 10 wherein the covering insulation layer is phospho-silicate glass.
Claim 15
Dependent Claim
17 words
12 . A method as defined in claim 10 wherein the covering insulation layer is boro-phospho-silicate glass.
Claim 16
Dependent Claim
97 words
13 . A method as defined in claim 9 wherein the active device providing step includes the steps of: A. depositing a gate insulation layer over the active device regions; B. forming gate electrodes on the gate insulation layer; C. using the field insulation layer and the gate electrodes as masks, implanting source and drain regions to form regions of a second conductivity type; and D. using the field insulation layer and the gate electrodes as masks, removing the gate insulation layer in the source and drain regions, the gate insulation layer beneath the gate electrodes remaining.
Claim 17
Dependent Claim
25 words
14 . A method as defined in claim 13 further comprising the step of providing source and drain power connections on the field insulation layer.
Claim 18
Dependent Claim
47 words
15 . A method as defined in claim 9 wherein the sidewall insulation layer step includes the steps of: A. covering the chip with an insulation layer; and B. etching the insulation layer sufficiently to expose the upper surfaces of the active device and field insulation layer.
Claim 19
Dependent Claim
20 words
A method as defined in claim 15 wherein the sidewall insulation layer is silicon dioxide deposited using chemical vapor deposition.
Claim 20
Dependent Claim
19 words
A method as defined in claim 16 wherein the etching step is performed using a directional reactive ion etch.
Claim 21
Dependent Claim
83 words
A method as defined in claim 9 wherein the conductive material deposition step comprises the steps of: A. depositing a layer of conductive material over the surface of the chip, the conductive material layer being substantially planar in the active device regions; and B. etching the conductive material so as to leave conductive material in the recesses such that the upper surfaces of the conductive material is at the level of the upper surfaces of the gate electrodes and the field insulation layer.
References Cited (Backward Citations)
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