EP0162718A2
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EP
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Digital signal translation circuit
Assignee: Advanced Micro Devices Inc
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Filing: 1985-05-23
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Granted: —
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Expires: 2005-05-23
Abstract
Abstract Disclosed is a digital signal translation circuit for translating a first type signal to a second type signal which comprises a master latch and a slave latch. The master latch latches the incoming first type signal during a first portion of the clock signal. A slave latch latches the master latch output and generates a differential output. The differential output of the slave drives an output driver circuit which generates the second type signal.
Inventors
- 👤 Michael Allen
- 👤 Tsen-Shau Yang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 16:38
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/289
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
117 words
An apparatus for translating a first type signal to a second type signal, the apparatus being responsive to a clock signal, comprising: (a) master latch means for latching the first type signal during a portion of the clock signal and for generating a master latch signal corresponding to the level of the first type signal; (b) slave latch means for latching the master latch signal and for generating a slave latch signal; (c) lookahead means, responsive to the master latch signal, for switching the slave latch signal before said slave latch means completes a latch of the master latch signal; and (d) output driver means, responsive to the slave latch signal, for supplying the second type signal.
Claim 2
Independent Claim
117 words
An apparatus for translating a first type signal to a second type signal, the apparatus being responsive to a clock signal, comprising: (a) master latch means for latching the first type signal during a portion of the clock signal and for generating a master latch signal corresponding to the level of the first type signal; (b) slave latch means for latching the master latch signal and for generating a slave latch signal; (c) lookahead means, responsive to the master latch signal, for switching the slave latch signal before said slave latch means completes a latch of the master latch signal; and (d) output driver means, responsive to the slave latch signal, for supplying the second type signal.
Claim 3
Dependent Claim
108 words
The apparatus of Claim 1, wherein: said slave latch signal is a differential signal, the differential signal including a first voltage signal and a second voltage signal and having a first state when the first voltage signal is higher than the second voltage signal and having a second state when the second voltage signal is higher than the first voltage signal, and said output driver means includes a differential pair of transistors, one of said differential pair being turned on when the differential signal is in the first state and the other of said differential pair being turned on when the differential signal is in the second state.
Claim 4
Dependent Claim
17 words
The apparatus of Claim 2, including: means for maintaining a minimum static level in the differential signal.
Claim 5
Dependent Claim
17 words
The apparatus of Claim 2, including: means for maintaining a desired voltage swing in said differential signal.
Claim 6
Independent Claim
183 words
An apparatus for translating a first type digital signal to a corresponding second type digital signal, the apparatus being responsive to a clock signal, comprising: (a) master latch means for latching the first type digital signal during a portion of the clock signal and for generating a master latch signal corresponding to the level of the first type digital signal; (b) slave latch means, for latching said master latch signal and for generating a differential signal, the differential signal including a first voltage signal and a second voltage signal and having a first state when the first voltage signal is higher than the second voltage signal and having a second state when the second voltage signal is higher than the first voltage signal, the state of the differential signal corresponding to the first type digital signal; (c) lookahead means, responsive to the master latch signal, for switching the state of the differential signal before said slave latch means completes a latch of the master latch signal; and (d) output driver means responsive to the differential signal, for supplying the second type digital signal.
Claim 7
Independent Claim
183 words
An apparatus for translating a first type digital signal to a corresponding second type digital signal, the apparatus being responsive to a clock signal, comprising: (a) master latch means for latching the first type digital signal during a portion of the clock signal and for generating a master latch signal corresponding to the level of the first type digital signal; (b) slave latch means, for latching said master latch signal and for generating a differential signal, the differential signal including a first voltage signal and a second voltage signal and having a first state when the first voltage signal is higher than the second voltage signal and having a second state when the second voltage signal is higher than the first voltage signal, the state of the differential signal corresponding to the first type digital signal; (c) lookahead means, responsive to the master latch signal, for switching the state of the differential signal before said slave latch means completes a latch of the master latch signal; and (d) output driver means responsive to the differential signal, for supplying the second type digital signal.
Claim 8
Dependent Claim
56 words
The apparatus of Claim 5, wherein said output driver means includes: a differential pair of transistors, one of said differential pair of transistors being turned on when the differential signal is in the first state and the other of said differential pair of transistors being turned on when the differential signal is in the second state.
Claim 9
Dependent Claim
55 words
The apparatus of Claim 5, wherein: said differential pair of transistors have emitters connected to a common emitter node, and a constant current source transistor supplying current through said common emitter node; and including means for maintaining a minimum static level in the differential signal sufficient to prevent saturation of said constant current source transistor.
Claim 10
Dependent Claim
50 words
The apparatus of Claim 5, including: a first voltage divider means coupled to said slave latch means for maintaining a minimum static level in the first voltage signal, and a second voltage divider coupled to said, slave latch means for maintaining a minimum static level in the second voltage sighal.
Claim 11
Dependent Claim
54 words
The apparatus of Claim 5, wherein said slave latch means include: a first semiconductor switch and a second semiconductor switch and wherein the difference in voltage between the first voltage signal and the second voltage signal is determined by the difference in voltage drop across said first semiconductor switch and said second semiconductor switch.
Claim 12
Dependent Claim
77 words
The apparatus of Claim 9, wherein said first and second semiconductor switches each include a first circuit path energized when said respective semiconductor switch is on and a second circuit path energized when said respective semiconductor switch is off, and said first circuit paths of said first and second semiconductor switches include means for increasing the voltage drop in said first circuit paths to maintain a desired difference in voltage across said first and second semiconductor switches.
Claim 13
Dependent Claim
96 words
The apparatus of Claim 5, wherein said lookahead means includes, first diode means coupled across the first voltage signal and the master latch signal to pull the first voltage signal to a level below the second voltage signal when the master latch signal indicates one level of the first type digital signal, and second diode means coupled across the second voltage signal and the master latch signal to pull down the second voltage signal below the level of the first voltage signal when the master latch signal indicates another level of the first type digital signal.
Claim 14
Independent Claim
174 words
An apparatus for storing a TTL signal and providing a corresponding ECL signal, the apparatus being responsive to a clock signal, comprising: (a) master latch means for latching the TTL signal during a portion of the clock signal and for generating a master latch signal corresponding to the TTL signal; (b) slave latch means, for latching the master latch signal to store the TTL signal and for generating a differential signal, the differential signal including a first voltage signal and a second voltage signal and having a first state when the first voltage signal is higher than the second voltage signal and having a second state when the second voltage signal is higher than the first voltage signal, the state of the differential signal corresponding to the TTL signal; (c) lookahead means, responsive to the master latch signal, for switching the state of the differential signal before said slave latch means completes a latch of the master latch signal; and (d) output driver means, responsive to the differential signal, for supplying the ECL signal.
Claim 15
Independent Claim
174 words
An apparatus for storing a TTL signal and providing a corresponding ECL signal, the apparatus being responsive to a clock signal, comprising: (a) master latch means for latching the TTL signal during a portion of the clock signal and for generating a master latch signal corresponding to the TTL signal; (b) slave latch means, for latching the master latch signal to store the TTL signal and for generating a differential signal, the differential signal including a first voltage signal and a second voltage signal and having a first state when the first voltage signal is higher than the second voltage signal and having a second state when the second voltage signal is higher than the first voltage signal, the state of the differential signal corresponding to the TTL signal; (c) lookahead means, responsive to the master latch signal, for switching the state of the differential signal before said slave latch means completes a latch of the master latch signal; and (d) output driver means, responsive to the differential signal, for supplying the ECL signal.
Claim 16
Dependent Claim
75 words
The apparatus of Claim 12, wherein said output driver means includes: a differential pair of transistors, one of said differential pair of transistors being turned on when the differential signal is in the first state and the other of said differential pair of transistors being turned on when the differential signal is in the second state; and an emitter follower output driver circuit connected to one of said differential pair for providing the ECL signal.
Claim 17
Dependent Claim
51 words
The apparatus of Claim 12, including: a first voltage divider means, coupled to said slave latch means, for maintaining a minimum static level in the first voltage signal, and a second voltage divider means, coupled to said slave latch means, for maintaining a minimum static level in the second voltage signal.
Claim 18
Dependent Claim
15 words
The apparatus of Claim 12, wherein: said apparatus is formed on a single semiconductor chip.
References Cited (Backward Citations)
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