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EP0162231A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Multi-function CPU having interface

Assignee: ASCII Corp
•
Filing: 1985-03-26
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Granted: —
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Expires: 2005-03-26
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Abstract

Abstract A keyboard interface is disclosed which, when a keyboard matrix (23) and an LED driver IC (19) are connected to a multi- function CPU (11), by outputting a scan signal and reading out a return signal through a bus line (17), can reduce the number of pins to its minimum and thus can increase pins having different functions. A printer Interface is also disclosed which, when a printer is connected to a multi-function CPU, with addition of a date register, can increase the functions of the multi-function CPU under the limited number of pins by specifying a level mode or a printer strobe mode. The keyboard and printer interfaces are respectively capable of expanding the functions of the multi-function CPU (11) further by providing a port for requesting an interrupt as well as a register having an enable bit to inhibit such interrupt. The interfaces, when the functions of the multi-function CPU are further expanded, are adapted to be controllable systematically so as to prevent confusion by providing within the CPU a port to indicate the ID number of LSls.

Inventors

  • 👤 Takatoshi Ishii
  • 👤 Ryozo Yamashita

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 20:33
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/01; G06F3/02; G06F3/0227; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F3/12; G06F3/1201; G06F3/1202; G06F3/1203; G06F3/1207; G06F3/1223; G06F3/1229; G06F3/1236; G06F3/1278; G06F3/1279; G06F3/1284

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 58 words
A keyboard interface for a multi-function CPU (11) including a CPU (12) and its adjacent circuits (13,14, 15,16), characterised in that said keyboard interface uses a bi-directional bus line (17) to output a scan data signal of a keyboard matrix (23) as well as to read out a return signal of said keyboard matrix (23) (e.g. Fig. 2).
Claim 2
Dependent Claim 58 words
A keyboard interface for a multi-function CPU (11) including a CPU (12) and its adjacent circuits (13,14, 15,16), characterised in that said keyboard interface uses a bi-directional bus line (17) to output a scan data signal of a keyboard matrix (23) as well as to read out a return signal of said keyboard matrix (23) (e.g. Fig. 2).
Claim 3
Dependent Claim 59 words
A keyboard interface as defined in claim 1, characterised in that said keyboard interface writes said scan data signal, thereafter inhibits the output of said return signal by means of an internal bus switch signal (24a) to output said scan data signal, and outputs a keyboard strobe signal (24) a predetermined time afterwards to read out said return signal.
Claim 4
Dependent Claim 46 words
A keyboard interface as defined in claim 1 or 2 characterised in that said multi-function CPU (11) incorporates an expansion interface function (32) and a basic interface function (31) therein and is able to switch said two functions therebetween by means of mode specification means (36).
Claim 5
Dependent Claim 62 words
A printer interface for a multi-function CPU (103) including a CPU (121) and its peripheral circuits, characterised in that said printer interface is provided with mode specification means (135) to specify one of a level mode using a level signal on a printer and a printer strobe mode using said level signal as a strobe signal (e.g. Fig. 7 and Fig. 10).
Claim 6
Dependent Claim 62 words
A printer interface for a multi-function CPU (103) including a CPU (121) and its peripheral circuits, characterised in that said printer interface is provided with mode specification means (135) to specify one of a level mode using a level signal on a printer and a printer strobe mode using said level signal as a strobe signal (e.g. Fig. 7 and Fig. 10).
Claim 7
Dependent Claim 49 words
A CPU interrupt control device, characterised by a port (210) for requesting an interrupt to check an input signal for its level status or multi-function CPU for its internal status and by a register (209) having a bit therein for disabling or enabling said interrupt request (e.g. Fig. 11).
Claim 8
Dependent Claim 49 words
A CPU interrupt control device, characterised by a port (210) for requesting an interrupt to check an input signal for its level status or multi-function CPU for its internal status and by a register (209) having a bit therein for disabling or enabling said interrupt request (e.g. Fig. 11).
Claim 9
Dependent Claim 30 words
The CPU interrupt control device as defined in claim 5, characterised in that said register is provided in a multi-function CPU including a CPU (201) and its adja= cent circuits.
Claim 10
Dependent Claim 28 words
A multi-function CPU including a CPU (201) and its adjacent circuits, characterised by a port (208) for holding the ID number of LSIs provided therein (e.g. Fig. 11).
Claim 11
Dependent Claim 28 words
A multi-function CPU including a CPU (201) and its adjacent circuits, characterised by a port (208) for holding the ID number of LSIs provided therein (e.g. Fig. 11).
Claim 12
Dependent Claim 16 words
A multi-function CPU characterised by an interface according to any one of claims 1 to 4.

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