Self contained array timing

Claim 2

A process for testing a READ/WRITE memory array (12) embedded within an integrated circuit device (11), said integrated circuit device including interconnected logic circuit means and memory array circuit means, said memory array circuit means including address latch circuit means (21), data input latch circuit means (20), and data output latch circuit means (22), characterized by using an on-chip timing control network circuit means (19), said timing control network circuit means having a trigger signal chip input (16), a Read control chip input (17) and a Write control chip input (18), said process comprising the following not critically timed steps: (a) select the WRITE mode for the array by conditioning the WRITE control input (18) of the timing control network (19); (b) place the desired memory address on address input lines (14) of the address latch circuit means (21); (c) place the desired data bits on data input lines (15) of the data input latch circuit means (20); and thereafter, (d) provide a trigger signal from off-chip to the trigger signal chip input (16) of the timing control network, whereby a WRITE timing sequence will be automatically generated by the timing control network and the desired data will be written into the memory array (12) at the desired address.

Claim 3

A process for testing a READ/WRITE memory array embedded within an integrated circuit device, as recited in claim 1, wherein subsequent to step (d) of claim 1 the following not critically timed steps are performed: (e) select the READ mode for the array by conditioning the READ control input (17) of the timing control network (19); (f) place said desired address on the address input lines (14) of the address latch circuit means; and thereafter, (g) provide a trigger signal from off-chip to the trigger signal chip input (16) of the timing control network, whereby a READ timing sequence will be automatically generated by the timing control network (19) and the output latches (22) will capture within a predetermined time the data stored in said desired address.

Claim 4

A memory array chip (11) containing an embedded array (12), characterized by a single on-chip timing control network (19) which in response to a trigger signal from off-chip provides timing signals to test said embedded array.

Claim 5

A memory array chip (11) containing an embedded array (12), characterized by a single on-chip timing control network (19) which in response to a trigger signal from off-chip provides timing signals to test said embedded array.

Claim 6

A memory array chip containing an embedded array, as recited in claim 3, wherein said single on-chip timing control network (19) consists essentially of interconnected Inverter and And logic blocks.

Claim 7

An integrated circuit chip, containing a memory array (12), said memory array including: a plurality of memory elements for storing binary data, said stored binary data being arranged within said array at a plurality of addressable locations; controllable write circuit means for writing data into storage at a predetermined address within said array; and controllable read circuit means for reading data stored at a predetermined address within said array; said chip further containing: gated address latch circuit means (21) coupled to said controllable write circuit means and said controllable read circuit means, said gated address circuit means providing said predetermined address to said write circuit means or said read circuit means; gated data input latch circuit means (20) coupled to said controllable write circuit means, said gated input latch circuit means providing data to be written into storage at said predetermined address provided by said gated address latch circuit means (21); and gated data output latch circuit means (22) coupled to said controllable read circuit means, said gated output latch circuit means receiving the binary data read from the predetermined address by said controllable read circuit means; and characterized by: timing control network means (19) coupled to and controlling said controllable write circuit means and said controllable read circuit means, said timing control network also being coupled to said gated address latch circuit means, said gated data input latch circuit means and said gated data output latch circuit means, said timing control network on said integrated circuit chip providing all timing control signals (45-48) for the operation of said memory array contained on said integrated circuit chip upon receipt of a trigger signal (16).

Claim 8

An integrated circuit chip, containing a memory array (12), said memory array including: a plurality of memory elements for storing binary data, said stored binary data being arranged within said array at a plurality of addressable locations; controllable write circuit means for writing data into storage at a predetermined address within said array; and controllable read circuit means for reading data stored at a predetermined address within said array; said chip further containing: gated address latch circuit means (21) coupled to said controllable write circuit means and said controllable read circuit means, said gated address circuit means providing said predetermined address to said write circuit means or said read circuit means; gated data input latch circuit means (20) coupled to said controllable write circuit means, said gated input latch circuit means providing data to be written into storage at said predetermined address provided by said gated address latch circuit means (21); and gated data output latch circuit means (22) coupled to said controllable read circuit means, said gated output latch circuit means receiving the binary data read from the predetermined address by said controllable read circuit means; and characterized by: timing control network means (19) coupled to and controlling said controllable write circuit means and said controllable read circuit means, said timing control network also being coupled to said gated address latch circuit means, said gated data input latch circuit means and said gated data output latch circuit means, said timing control network on said integrated circuit chip providing all timing control signals (45-48) for the operation of said memory array contained on said integrated circuit chip upon receipt of a trigger signal (16).

Claim 9

An integrated circuit chip, containing a memory array as recited in claim 5, wherein said timing control network (19) receives from off-chip at least a trigger signal (16) and a READ/WRITE control input (17, 18).

Claim 10

An integrated circuit chip, containing a memory array as recited in claim 5, wherein said timing control network only receives from off-chip a trigger signal (42) and a READ/WRITE control signal (41).

Claim 11

An integrated circuit chip, containing a memory array as recited in claim 6 or 7, wherein said timing control network (19) includes a trigger signal responsive tapped delay line.

Claim 12

An integrated circuit chip, containing a memory array as recited in claim 6 or 7, wherein said timing control network consists essentially of a serial chain of INVERTER circuits..

Claim 13

A process for writing data into a READ/WRITE memory array (12) embedded within an integrated circuit device (11), said integrated circuit device including interconnected logic circuit means and memory array circuit means, said memory array circuit means including address latch circuit means, data input latch circuit means, and data output latch circuit means, characterized by said integrated circuit device including a timing control network circuit means (19) having a trigger signal chip input, a Read control chip input and a Write control chip input, and said process comprising the following not critically timed steps: (a) select the WRITE mode for the array by conditioning the WRITE control input of the timing control network; (b) place the desired memory address on address input lines of the address latch circuit means; (c) place the desired data bits on data input lines of the data input latch circuit means; and thereafter, (d) provide a trigger signal from off-chip to the trigger signal chip input of the timing control network, whereby a WRITE timing sequence will be automatically generated by the timing control network and the desired data will be written into the memory array at the desired address.

Claim 14

A process for writing data into a READ/WRITE memory array (12) embedded within an integrated circuit device (11), said integrated circuit device including interconnected logic circuit means and memory array circuit means, said memory array circuit means including address latch circuit means, data input latch circuit means, and data output latch circuit means, characterized by said integrated circuit device including a timing control network circuit means (19) having a trigger signal chip input, a Read control chip input and a Write control chip input, and said process comprising the following not critically timed steps: (a) select the WRITE mode for the array by conditioning the WRITE control input of the timing control network; (b) place the desired memory address on address input lines of the address latch circuit means; (c) place the desired data bits on data input lines of the data input latch circuit means; and thereafter, (d) provide a trigger signal from off-chip to the trigger signal chip input of the timing control network, whereby a WRITE timing sequence will be automatically generated by the timing control network and the desired data will be written into the memory array at the desired address.

Claim 15

A process for reading data from a READ/WRITE memory array embedded within an integrated circuit device, said integrated circuit device including interconnected logic circuit means and memory array circuit means, said memory array circuit means including address latch circuit means, data input latch circuit means, and data output latch circuit means, characterized by said integrated circuit device including a timing control network circuit means having a trigger signal chip input, a Read control chip input and a Write control chip input, and said process comprising the following not critically timed steps: (a) select the READ mode for the array by conditioning the READ control input of the timing control network; (b) place the desired memory address on address input lines of the address latch circuit means; and thereafter, (c) provide a trigger signal from off-chip to the trigger signal chip input of the timing control network, whereby a READ timing sequence will be automatically generated by the timing control network and the output latches will capture within a predetermined time the data stored at said desired address in said READ/WRITE memory array.

Claim 16

A process for reading data from a READ/WRITE memory array embedded within an integrated circuit device, said integrated circuit device including interconnected logic circuit means and memory array circuit means, said memory array circuit means including address latch circuit means, data input latch circuit means, and data output latch circuit means, characterized by said integrated circuit device including a timing control network circuit means having a trigger signal chip input, a Read control chip input and a Write control chip input, and said process comprising the following not critically timed steps: (a) select the READ mode for the array by conditioning the READ control input of the timing control network; (b) place the desired memory address on address input lines of the address latch circuit means; and thereafter, (c) provide a trigger signal from off-chip to the trigger signal chip input of the timing control network, whereby a READ timing sequence will be automatically generated by the timing control network and the output latches will capture within a predetermined time the data stored at said desired address in said READ/WRITE memory array.

Claim 17

An integrated circuit device contained on a semiconductor chip, said integrated circuit device including interconnected logic circuit means and memory array circuit means said memory array circuit means including address latch circuit means, data input latch circuit means, data output latch circuit means, and a READ/WRITE memory array, characterized by a timing control network (19), said timing control network interconnecting at least said address latch circuit means, said data input latch circuit means, said data output latch circuit means and said read/write memory array, said timing control network (19) in response to a trigger signal automatically providing a "WRITE" timing sequence for a "WRITE" mode of operation of said READ/WRITE memory array or a "READ" timing sequence for a "READ" mode of operation of said read/write memory array, said timing control network comprising: a control input terminal (43) adapted to receive a control signal from off-chip; a trigger input terminal (42) adapted to receive a trigger signal from off-chip; a read/write input terminal (41) adapted to receive a read/write signal from off-chip; an on-chip output terminal (48) connected to said output latch circuit means; an on-chip data input terminal (46) connected to said data input latch circuit means; an on-chip address terminal (45)connected to said address latch circuit means; an on-chip write clock terminal (47) connected to said read/write memory array; n serially connected INVERTER circuits (2-16), where n is an odd integer, said n serially connected INVERTER circuits forming a delay circuit having an input, an output and at least first, second, third and fourth (time displaced) spaced apart taps; a single INVERTER circuit (27) having an input connected to said read/write input terminal of said timing control network and an output; a first AND-INVERTER circuit (28) having a first input connected to said trigger input terminal of said timing control network, a second input, and an output connected to said input of said delay circuit formed by said n serially connected INVERTER circuits; a second AND-INVERTER circuit (31) having a first input connected to said control input terminal of said timing control network, a second input connected to said output of said delay circuit formed by said n serially connected INVERTER circuits and an output connected to said second input of said first AND-INVERTER circuit (28); a first OR-INVERTER circuit (26) having a first input connected to said read/write input terminal (41) of said timing control network, a second input connected to said output of said first AND-INVERTER circuit (28), a third input connected to said second tap on said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip data input terminal (46) of said timing control network; a second OR-INVERTER circuit (25) having a first input connected to said output of said first AND-INVERTER circuit (28), a second input connected to said second tap on said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip address terminal (45) of said timing control network; a third OR-INVERTER circuit (23) having a first input connected to said read/write input terminal (41) of said timing control network (19), a second input connected to said first tap on said delay circuit formed by said n serially connected INVERTER circuits, a third input connected to said third tap on said delay circuit formed by said n serially connected delay circuits and an output connected to said on-chip write clock terminal (47) of said timing control network; and, a fourth OR-INVERTER circuit (24) having a first input connected to said output of said single INVERTER circuit (27), a second input connected to said fourth tap of said delay circuit formed by said n serially connected INVERTER circuits, a third input connected to said output of said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip data output terminal (48) of said timing control network.

Claim 18

An integrated circuit device contained on a semiconductor chip, said integrated circuit device including interconnected logic circuit means and memory array circuit means said memory array circuit means including address latch circuit means, data input latch circuit means, data output latch circuit means, and a READ/WRITE memory array, characterized by a timing control network (19), said timing control network interconnecting at least said address latch circuit means, said data input latch circuit means, said data output latch circuit means and said read/write memory array, said timing control network (19) in response to a trigger signal automatically providing a "WRITE" timing sequence for a "WRITE" mode of operation of said READ/WRITE memory array or a "READ" timing sequence for a "READ" mode of operation of said read/write memory array, said timing control network comprising: a control input terminal (43) adapted to receive a control signal from off-chip; a trigger input terminal (42) adapted to receive a trigger signal from off-chip; a read/write input terminal (41) adapted to receive a read/write signal from off-chip; an on-chip output terminal (48) connected to said output latch circuit means; an on-chip data input terminal (46) connected to said data input latch circuit means; an on-chip address terminal (45)connected to said address latch circuit means; an on-chip write clock terminal (47) connected to said read/write memory array; n serially connected INVERTER circuits (2-16), where n is an odd integer, said n serially connected INVERTER circuits forming a delay circuit having an input, an output and at least first, second, third and fourth (time displaced) spaced apart taps; a single INVERTER circuit (27) having an input connected to said read/write input terminal of said timing control network and an output; a first AND-INVERTER circuit (28) having a first input connected to said trigger input terminal of said timing control network, a second input, and an output connected to said input of said delay circuit formed by said n serially connected INVERTER circuits; a second AND-INVERTER circuit (31) having a first input connected to said control input terminal of said timing control network, a second input connected to said output of said delay circuit formed by said n serially connected INVERTER circuits and an output connected to said second input of said first AND-INVERTER circuit (28); a first OR-INVERTER circuit (26) having a first input connected to said read/write input terminal (41) of said timing control network, a second input connected to said output of said first AND-INVERTER circuit (28), a third input connected to said second tap on said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip data input terminal (46) of said timing control network; a second OR-INVERTER circuit (25) having a first input connected to said output of said first AND-INVERTER circuit (28), a second input connected to said second tap on said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip address terminal (45) of said timing control network; a third OR-INVERTER circuit (23) having a first input connected to said read/write input terminal (41) of said timing control network (19), a second input connected to said first tap on said delay circuit formed by said n serially connected INVERTER circuits, a third input connected to said third tap on said delay circuit formed by said n serially connected delay circuits and an output connected to said on-chip write clock terminal (47) of said timing control network; and, a fourth OR-INVERTER circuit (24) having a first input connected to said output of said single INVERTER circuit (27), a second input connected to said fourth tap of said delay circuit formed by said n serially connected INVERTER circuits, a third input connected to said output of said delay circuit formed by said n serially connected INVERTER circuits, and an output connected to said on-chip data output terminal (48) of said timing control network.

Claim 19

An integrated circuit device contained on a semiconductor chip, as recited in 14, wherein said timing control network (19) further includes: a test output terminal (44) for providing an off-chip test signal; and, buffer amplifier circuit means (32) having an input connected to said output of said delay circuit formed by said n serially connected delay circuits and an output connected to said test output terminal (44) of said timing control.

Claim 20

An integrated circuit device contained on a semiconductor chip, as recited in 14, wherein said timing control network (19) further includes: a test output terminal (44) for providing an off-chip test signal; and, buffer amplifier circuit means (32) having an input connected to said output of said delay circuit formed by said n serially connected delay circuits and an output connected to said test output terminal (44) of said timing control.