Integrated circuit compatible thin film field effect transistor and method of making same

Claim 2

A thin film field effect transistor (10;30;50) of the type having a body (14;34;54) of semiconductor material, source (16;36;56) and drain (18;38;58) electrodes forming rectifying contacts with said body, and a gate electrode (22;42;62) adjacent to and insulated from said body, characterized by being an integrated circuit compatable thin film transistor in which said body is formed of a silicon-germanium alloy having a structure more ordered than amorphous silicon-germanium semiconductor material and less ordered than single crystalline semiconductor material.

Claim 3

The thin film field effect transistor (10) as defined in claim 1 further characterized by said source (16) and drain (18) electrodes being formed by doped regions in said body (14), with said body being of one conductivity type and said doped regions (16, 18) being of the opposite conductivity type.

Claim 4

The thin film field effect transistor (30;50) as defined in claim 1 further characterized by said source (36;56) and drain (38;58) electrodes being formed on said body (34;54).

Claim 5

The thin film field effect transistor (30) as defined in claim 3 further characterized by said source (36) and drain (38) electrodes being deposits of a metal on said body (34) and by said metal (36;38) being of a type which forms a rectifying Schottky barrier junction with said body of germanium semiconductor material.

Claim 6

The thin film field effect transistor (50) as defined in claim 3 further characterized by said source (56) and drain (58) electrodes being deposits of a doped semiconductor on said body (54).

Claim 7

The thin film field effect transistor (50) as defined in claim 5 further characterized by said doped semiconductor (56;58) being an amorphous semiconductor alloy.

Claim 8

The thin film field effect transistor (50) as defined in claim 5 further characterized by said amorphous semiconductor alloy (56;58) including silicon.

Claim 9

The thin film field effect transistor (50) as defined in claim 7 further characterized by said amorphous silicon alloy (56;58) including hydrogen or fluorine.

Claim 10

The thin film field effect transistor (50) as defined in claim 5 further characterized by said body (54) being of a first conductivity type and said doped semiconductor (56;58) being of the opposite conductivity type.

Claim 11

The thin film field effect transistor (10;30;50) as defined in claim 1 further characterized by said body (14;34;54) further including hydrogen or fluorine.

Claim 12

The thin film field effect transistor (10;30;50) as defined in claim 1 further characterized by said body (14;34;54) further including fluorine.

Claim 13

An improved system (70) for selectively addressing each element (96) of an array of elements, said system being of the type having a first set of address lines (72,74,76,78,80,82), a second set of address lines (84,86,88,90,92) spaced from and crossing at an angle to said first set of address lines to form a plurality of crossover points (94) therewith, each such crossover point being associated with a given one of said elements to be addressed, an isolation device (98) associated with each said element to be addressed, and addressing circuitry (102,104) coupled to said first and second sets of address lines for selectively applying addressing potentials to respective pairs of said first and second sets of address lines; such system being characterized by said addressing circuitry including at least one integrated circuit compatible thin film field effect transistor (10;30;50) comprising a silicon-germanium alloy body (14;34;54), said body having a structure more ordered than amorphous silicon-germanium semiconductor material and less ordered than single crystalline semiconductor material, source (16;36;56) and drain (18;38;58) electrodes formed by rectifying contacts with said body, and a gate electrode (22;42;62) adjacent to and insulated from said body.

Claim 14

An improved system (70) for selectively addressing each element (96) of an array of elements, said system being of the type having a first set of address lines (72,74,76,78,80,82), a second set of address lines (84,86,88,90,92) spaced from and crossing at an angle to said first set of address lines to form a plurality of crossover points (94) therewith, each such crossover point being associated with a given one of said elements to be addressed, an isolation device (98) associated with each said element to be addressed, and addressing circuitry (102,104) coupled to said first and second sets of address lines for selectively applying addressing potentials to respective pairs of said first and second sets of address lines; such system being characterized by said addressing circuitry including at least one integrated circuit compatible thin film field effect transistor (10;30;50) comprising a silicon-germanium alloy body (14;34;54), said body having a structure more ordered than amorphous silicon-germanium semiconductor material and less ordered than single crystalline semiconductor material, source (16;36;56) and drain (18;38;58) electrodes formed by rectifying contacts with said body, and a gate electrode (22;42;62) adjacent to and insulated from said body.

Claim 15

The system (70) as defined in claim 12 further characterized by said source (16) and drain (18) electrodes of said thin film field effect transistor (10) being formed in said body (14).

Claim 16

The system (70) as defined in claim 13 further characterized by said source (16) and drain (18) electrodes being formed by doped regions in said body (14) and by said body being of one conductivity type and said doped regions being of opposite conductivity type.

Claim 17

The system (70) as defined in claim 12 further characterized by said source (36;56) and drain (38;58) electrodes of said thin film field effect transistor (30;50) being formed on said body (34;54).

Claim 18

The system (70) as defined in claim 15 further characterized by said source (36) and drain (38) electrodes being deposits of a metal on said body (34) and by said metal being of a type which forms a rectifying Schottky barrier junction with said body (34) of germanium semiconductor material.

Claim 19

The system (70) as defined in claim 15 further characterized by said source (56) and drain (58) electrodes being deposits of a doped semiconductor on said body (54).

Claim 20

The system (70) as defined in claim 17 further characterized by said doped semiconductor (56;58) being an amorphous semiconductor alloy.

Claim 21

The system (70) as defined in claim 18 further characterized by said amorphous semiconductor alloy (56;58) including silicon.

Claim 22

The system (70) as defined in claim 19 further characterized by said amorphous silicon alloy (56;58) including hydrogen or fluorine.

Claim 23

The system (70) as defined in claim 17 further characterized by said body (54) being of a first conductivity type and said doped semiconductor (56;58) being of an opposite conductivity type.

Claim 24

The system (70) as defined in claim 12 further characterized by said body (14;34;54)'of said thin film field effect transistor (10;30;50) further including hydrogen.

Claim 25

The system (70) as defined in claim 12 further characterized by said body (14;34;54) of said thin film field effect transistor (10;30;50) further including fluorine.

Claim 26

The system (70) as defined in claim 12 further characterized by said isolation devices being thin film field effect transistors (98) including amorphous semiconductor alloy materials.

Claim 27

The system (70) as defined in claim 12 further characterized by said isolation devices (98) and said addressing circuitry (102;104), including said integrated circuit compatable thin film field effect transistor (10;30;50), are formed on a common substrate (12;32;52).

Claim 30

The method as defined in claim 26 further characterized by said body (14;34;54) being formed by depositing said silicon-germanium alloy onto a substrate (12;32;52) and further characterized by said substrate being heated to a temperature between 2 30 0 and 350 0 C during the deposition of said alloy.

Claim 31

The method as defined in claim 27 further characterized by forming said body (14;34;54) by vapor deposition.

Claim 32

The method as defined in claim 28 further characterized by depositing said body (14;34;54) by vacuum evaporation.

Claim 33

The method as defined in claim 26 further characterized by the step of annealing said body (14;34;54) prior to forming said drain (18;38;58) and source (16;36;56).

Claim 34

The method as defined in claim 30 further characterized by annealing said body (14;34;54) in a hydrogen gas atmosphere.

Claim 35

The method as defined in claim 31 further characterized by annealing said body (14;34;54) at a temperature of about 350°C.

Claim 36

The method as defined in claim 30 further characterized by annealing said body (14;34;54) in an atmosphere of a hydrogen gas and a forming gas.

Claim 37

The method as defined in claim 33 further characterized by said forming gas being nitrogen.

Claim 38

The method as defined in claim 33 further characterized annealing said body (13;34;54) at a temperature of about 350°C.

Claim 39

The method as defined in claim 30 further characterized by annealing said body (13;34;54) in a hydrogen plasma.

Claim 40

The method as defined in claim 30 further characterized by annealing said body (13;34;54) in a fluorine plasma.

Claim 41

The method as defined in claim 37 further characterized by annealing said body (13;34;54) at a temperature of about 350°C

Claim 42

The method as defined in claim 26 further characterized by said step of forming said source (16) and drain (18) electrodes including forming said electrodes in said body (14).

Claim 43

The method as defined in claim 39 further characterized by forming said source (16) and drain (18) electrodes by doping separated regions with a dopant in said body (14).

Claim 44

The method as defined in claim 39 further characterized by forming said body (14) to be of a first conductivity type and said dopant to be a dopant which tends to make the semiconductor material of said body be of the opposite conductivity type.

Claim 45

The method as defined in claim 26 further characterized by said step of forming said source (36;56) and drain (38;58) electrodes including forming said electrodes on said body (34;54).

Claim 46

The method as defined in claim 42 further characterized by forming said source (36) and drain (38) electrodes by depositing a metal in at least two spaced apart regions on said body (34) and by said metal being of a type which forms a rectifying Schottky barrier junction with said body.

Claim 47

The method as defined in claim 42 further characterized by forming said source (56) and drain (58) electrodes by depositing a doped semiconductor in at least two spaced apart regions on said body (54).

Claim 48

The method as defined in claim 44 further characterized by said doped semiconductor (56,58) being an amorphous semiconductor alloy.

Claim 49

The method as defined in claim 45 further characterized by said amorphous semiconductor alloy (56,58) including silicon.

Claim 50

The method as defined in claim 46 further characterized by said amorphous silicon alloy (56,58) including hydrogen or fluorine.