EP0160392A2
Expired / Lapsed
EP
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Semiconductor memory device having double layered word lines
Assignee: Toshiba Corp
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Filing: 1985-03-26
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Granted: —
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Expires: 2005-03-26
Abstract
Abstract According to a memory of the invention which can read/write data, word lines (16) are connected to memory cells arranged on a semiconductor substrate (12). Each word line (16) has a double layered structure comprising first and second conductive lines (16-1, 16-2). An insulative layer (70) is sandwiched between the conductive lines (16-1, 16-2). Since the insulative layer (70) has a plurality of contact holes (C1 to C9) formed along the extended direction of the first and second lines and spared by an irregular pitch, the stacked lines (16-1, 16-2) are discontinuously and electrically connected to each other through these contact holes (C1 to C9).
Inventors
- 👤 Yasuo C/O Patent Division Itoh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 21:40
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/435; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
350 words
A semiconductor memory device comprising: a plurality of memory cells (10), which are formed on a semiconductor substrate (12), each having a memory cell transistor (18) and a memory cell capacitor (20) which is charged so as to reflect the logic state of its memory cell, and address lines (14, 16) which extend in row and column directions on said semiconductor substrate and select the particular memory cell for reading/writing data from/in the desired memory cell, characterized in that said address lines include double layered address lines (16) each of which comprises, first and second conductive lines (42, 60; 16-1, 16-2) each of which has a first end portion for receiving a voltage signal for selecting the particular memory cell and a second end portion at an opposite side of said first end portion, which are stacked, and which extend in one of the row and column directions, and a linear insulative layer which extends along an extending direction of said first and secono conductive lines (42, 60; 16-1, 16-2), is sanowiched between said first and second conductive lines (42, 60; 16-1, 16-2), has contact holes (Cl to C9) formed along the extending direction of said first and second conductive lines (42, 60; 16-1, 16-2), and allows electrical connection between said first and second conductive lines (42, 60; 16-1, 16-2) through the contact holes (C1 to C9), and that an interval of two neighbouring contact holes (C8 and C9) at the second end portion of each of said first and second conductive lines (42, 60; 16-1, 16-2) is set to be smaller than that of two neighbouring contact holes (C1 and C2) at the first end portion of each of said first and second conductive lines (42, 60; 16-1, 16-2), thereby decreasing the maximum delay time in signal transfer at the second end portion of each of said double layered address lines, and the interval between two neighbouring contact holes at the first end portion of each of said first and second conductive lines is increased, thereby avoiding an increase in the total number of contact holes (C1 to C9).
Claim 2
Dependent Claim
350 words
A semiconductor memory device comprising: a plurality of memory cells (10), which are formed on a semiconductor substrate (12), each having a memory cell transistor (18) and a memory cell capacitor (20) which is charged so as to reflect the logic state of its memory cell, and address lines (14, 16) which extend in row and column directions on said semiconductor substrate and select the particular memory cell for reading/writing data from/in the desired memory cell, characterized in that said address lines include double layered address lines (16) each of which comprises, first and second conductive lines (42, 60; 16-1, 16-2) each of which has a first end portion for receiving a voltage signal for selecting the particular memory cell and a second end portion at an opposite side of said first end portion, which are stacked, and which extend in one of the row and column directions, and a linear insulative layer which extends along an extending direction of said first and secono conductive lines (42, 60; 16-1, 16-2), is sanowiched between said first and second conductive lines (42, 60; 16-1, 16-2), has contact holes (Cl to C9) formed along the extending direction of said first and second conductive lines (42, 60; 16-1, 16-2), and allows electrical connection between said first and second conductive lines (42, 60; 16-1, 16-2) through the contact holes (C1 to C9), and that an interval of two neighbouring contact holes (C8 and C9) at the second end portion of each of said first and second conductive lines (42, 60; 16-1, 16-2) is set to be smaller than that of two neighbouring contact holes (C1 and C2) at the first end portion of each of said first and second conductive lines (42, 60; 16-1, 16-2), thereby decreasing the maximum delay time in signal transfer at the second end portion of each of said double layered address lines, and the interval between two neighbouring contact holes at the first end portion of each of said first and second conductive lines is increased, thereby avoiding an increase in the total number of contact holes (C1 to C9).
Claim 3
Dependent Claim
42 words
The device according to claim 1, characterized in that said first conductive line (16-1) comprises a polycrystalline silicon (42).connected to said memory cell transistors (18) formed on said semiconductor substrate (12), and said second conductive line (16-2) comprises a metal layer (60).
Claim 4
Dependent Claim
53 words
The device according to claim 2, characterized in that the contact holes (C1 to C9) are formed in said linear insulative layer (70) such that an interval between each two neighbouring contact holes is decreased from the first end portion to the second end portion of each of said double layered address lines.
Claim 5
Dependent Claim
87 words
.The device according to claim 3, characterized in that the interval between each two neighbouring contact holes among the contact holes (C1 to C9) is selected in such a manner that a plurality of delay time peak values in signal transfer of said double layered address lines obtained between each two neighbouring contact holes coincide with a predetermined delay level, whereby the maximum delay time in signal transfer of said memory device can be minimized while avoiding an increase in the total number of the contact holes.
Claim 6
Dependent Claim
23 words
The device according to claim 4, characterized in that said double layered address lines correspond to word lines (16) in said memory device.
References Cited (Backward Citations)
No citation records indexed.
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