EP0159712A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Control means in a digital computer
Assignee: Bull HN Information Systems Inc
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Filing: 1985-04-25
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Granted: —
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Expires: 2005-04-25
Abstract
Abstract A directory unit includes means for storing address and control data relating to a plurality of cache transactions during the interval between the initiation of the individual ones of the transactions and the completion thereof. The directory includes the capability of comparing the pertinent data relative to subsequent proposed transaction with the corresponding data stored in the directory to determine if a procedural conflict exists, and, in the event of a conflict to issue control signals to resolve the conflict. Additionally, the address and control data stored in the directory is accessed to control the storage of a completed CPU operation into the appropriate location in the cache memory.
Inventors
- 👤 Gregory C. Edgington
- 👤 Daniel M. Mccarthy
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 03:12
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3812; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0828; G06F12/0844; G06F12/0855
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
64 words
In a computer system which includes a central processor unit and a memory system, wherein said central processor unit includes a cache memory which is operated on a store-into-cache basis and wherein said central processor is operated on a pipeline protocol, control means for controlling the data flow in such a system to avoid implementation of conflicting instructions in the pipeline, said means comprising:
Claim 2
Dependent Claim
128 words
a memory array having a plurality of addressable locations; means for storing in said array, at selected address locations, address and function flag information related to each instruction currently in said pipeline; means for comparing address information relative to each new instruction with address informaiton in said array to detect the presence of previous instructions still in progress relating to the same data as said new instructions, to produce a HIT signal in the event of address coincidence; and means for evaluating the function flag information corresponding to a coincident address in said array to determine if implementation of said new instruciton would introduce a conflict, said means for evaluating including means to issue a BREAK signal to said computer system in the event a conflict is indicated.
Claim 3
Dependent Claim
28 words
Claim 2. Control means for a computer system as set forth in Claim 1 wherein said memory array includes sixteen addressable locations to accommodate up to sixteen entries.
Claim 4
Dependent Claim
34 words
Claim 3 Control means for a computer system as set forth in Claim 1 wherein said memory array includes addressable locations which are address related to selected digets of said address information stored therein.
Claim 5
Dependent Claim
39 words
Claim 4 Control means for a computer system as set forth in Claim 1 wherein means are provided for receiving said address information relative to said new instructions selectively from said central processor unit or from said memory system.
Claim 6
Dependent Claim
30 words
Claim 5 Control means for a computer system as set forth in Claim 4 wherein said array includes a plurality levels with each level having a plurality of entry sets.
Claim 7
Dependent Claim
35 words
Claim 6 Control means for a computer system as set forth in Claim 5 wherein said array includes four levels with each level including four entry sets, said levels and said sets being separately addressable.
Claim 8
Dependent Claim
42 words
Ciaim 7 Control means for a computer system as set forth in Claim 6 wherein said comparing means includes output selector means associated, respectively, with each of said levels to effect a controlled selection of the address information the associated entry sets
Claim 9
Dependent Claim
42 words
claim a Control means for a computer system as set forth in Claim 7 wherein said comparing means further includes a comparator means connected to compare the selected output address information from said array with said address information of said new instruction.
Claim 10
Dependent Claim
51 words
Claim 9 Control means for a computer system as set forth in Claim 8 wherein said output selector means associated with each of said levels includes a plurality of selector units, each of said plurality of selector units being connected to be enable, respectively, by address signals from a different source.
Claim 11
Dependent Claim
78 words
Claim 10 Control means for a computer system as set forth in Claim 9 wherein said central processor unit further includes an instruction-fetch unit, and wherein said plurality selector units include a first selector unit connected to respond to address information signals from said instruction-fetch unit, a second selector unit connected to respond to pipelined address information signals from said cache memory and a third selector unit connected to respond to address information signals from said memory system.
Claim 12
Dependent Claim
41 words
Claim 11 Control means for a computer system as set forth in Claim 10 wherein said means for evaluating includes further output selector means associated, respectively, with each of said levels to effect a controlled selection of said function flag information.
Claim 13
Dependent Claim
81 words
Claim 12 Control means for a computer b ystem as set forth in Claim 11 wherein said further output selector means associated, respectively, with each of said levels includes a first selector unit connected to respond to function flag information control signals from said instruction-fetch unit, a second selector unit connected to respond to function flag information contrbl signals from said cache memory, and a third selector unit connected to respond to function flag information control signals from said memory system.
Claim 14
Dependent Claim
37 words
Claim 13 Control means for a computer system as set forth in Claim 12 wherein said evaluating means further includes BREAK signal logic means connected to respond to said selected function flag information and said HIT signals.
Claim 15
Dependent Claim
92 words
Claim 14 Control means for a computer system as set forth in Claim 13 wherein said BREAK signal logic means includes a first BREAK signal logic unit connected to respond to said HIT signals and said selected function flag information signals from said instruction-fetch unit, a second BREAK signal logic unit connected to respond to said HIT signals and said selected function flag information signal from cache memory, and a third BREAK signal logic unit connected to relspond to said HIT signals and said selected flag informations signals from said memory system.
Claim 16
Dependent Claim
83 words
Claim 15 Control means for a computer system as set forth in Claim 1 characterized by the addition of means, responsive to a control signal from said centrol processor unit indicative that data manipulated by said central processor unit is ready for storage into said cache, for selecting the address associated the data from said address information stored in said array, and means for transmitting the selected address to said cache to effect the storage of said data at the indicated address therein.
Claim 17
Dependent Claim
66 words
Claim 16 In a computer system which includes a central processor unit and a memory system, wherein said central processor unit includes a chache memory unit which is operated on a store-into-cache bases and wherein said central processor is operated on a pipeline protocol, a method of controlling the data flow in said system to avoid implementation of conflicting instructions in the pipeline, said method comprising:
Claim 18
Dependent Claim
102 words
storing at addressable locations in a memory array address and function flag information related to each instruction currently in said pipeline comparing address informaiton relative to each new instruction with address information stored in said array to detect the presence of previous instructions relating to the same data as said new instruction; producing a HIT signal in the event of an address coincidence; evaluating said function flag information identified with said BIT signal to determine if the implementation of said new instruction would a conflict; and issuing a BREAK signal to said computer system in the event such a conflict is indicated.
References Cited (Backward Citations)
No citation records indexed.
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