EP0157428A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device with low-noise structure
Assignee: NEC Corp
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Filing: 1985-04-04
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Granted: —
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Expires: 2005-04-04
Abstract
Abstract A semiconductor memory device which has low noise structure and is operable with high stability. The memory device employes a plurality of single transistor memory cells each composed of a capacitor and a transistor coupled between one electrode of the capacitor and a bit line, the other electrode of the capacitor being supplied with a predetermined potential. The other electrode is made of a refractory metal and a relatively low sheet resistance is provided to the other electrode of the capacitor so that the potential fluctuation at the other electrode of the capacitor is suppressed.
Inventors
- 👤 Tatsunori Murotani
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 16:49
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/047; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H10B; H10B12/00; H10B12/30; H10D1/60; H10D1/68
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
104 words
A semiconductor memory device of the type having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each of said memory cells including a capacitor having a first electrode supplied with a predetermined potential and a second electrode and a field effect transistor coupled between said second electrode of said capacitor and one of said bit lines with its drain-source current path and having a gate coupled to one of said word lines, wherein said first electrode of said capacitor includes a conductive layer of at least one of refractory metal and silicide of said refractory metal.
Claim 2
Dependent Claim
104 words
A semiconductor memory device of the type having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each of said memory cells including a capacitor having a first electrode supplied with a predetermined potential and a second electrode and a field effect transistor coupled between said second electrode of said capacitor and one of said bit lines with its drain-source current path and having a gate coupled to one of said word lines, wherein said first electrode of said capacitor includes a conductive layer of at least one of refractory metal and silicide of said refractory metal.
Claim 3
Dependent Claim
19 words
The memory device according to claim 1, wherein the gate electrode of said transistor is formed of polycrystalline silicon.
Claim 4
Dependent Claim
27 words
The memory device according to claim 1, wherein said first electrode of said capcitor is made of a single consecutive pattern over a whole memory cell array.
Claim 5
Dependent Claim
22 words
The memory device according to claim 1, wherein each of said bit lines includes a diffusion region formed in a semiconductor substrate.
Claim 6
Dependent Claim
23 words
The memory device according to claim 1, wherein said refractory metal is selected from the group of molybdenum, tungsten, tantalum, niobium and titanium.
Claim 7
Dependent Claim
16 words
The memory device according to claim 1, further comprising an insulating layer covering said conductive layer.
Claim 8
Dependent Claim
38 words
The memory device according to claim 1, further comprising auxiliary of a highly-conductive metal formed over said conductive layer through an insulating layer, said auxiliary wiring being contacted with a plurality of different portions of said conductive layer.
Claim 9
Dependent Claim
97 words
In a semiconductor memory device comprising a semiconductor substrate, and a plurality of memory cells formed on said substrate, each of said memory cells including a field effect transistor and a charge storage capacitor coupled to said tranistor, one plate of each charge storage capacitor being couplead to said transistor, the other plates of the respective capacitors being commonly connected to a predetermined potential, the improvement comprising a conductive sheet of a refractory metal overlying on the region of said substrate where said memory cells are to be formed and defining the other plates of said capacitors.
Claim 10
Dependent Claim
97 words
In a semiconductor memory device comprising a semiconductor substrate, and a plurality of memory cells formed on said substrate, each of said memory cells including a field effect transistor and a charge storage capacitor coupled to said tranistor, one plate of each charge storage capacitor being couplead to said transistor, the other plates of the respective capacitors being commonly connected to a predetermined potential, the improvement comprising a conductive sheet of a refractory metal overlying on the region of said substrate where said memory cells are to be formed and defining the other plates of said capacitors.
Claim 11
Dependent Claim
27 words
The memory device according to claim 8, wherein said conductive sheet has a plurality of openings to expose at least a part of each of said transistors.
Claim 12
Dependent Claim
30 words
The memory device according to claim 9, wherein the gate of each of said transistors is formed of a polycrystalline silicon partially overlapping said conductive sheet via an insulating layer.
Claim 13
Dependent Claim
103 words
A semiconductor memory device comprising a semiconductor substrate, a plurality of memory cells formed on said substrate, each of said memory cells including a switch transistor and a storage capacitor coupled to said transistor with its first plate, a second plate of said capacitor being coupled to a predetermined potential, a conductive sheet formed on said semiconductor substrate and forming said second plates of a plurality of said capacitors, and a wiring of highly-conductive material formed on said conductive sheet via an insulating layer and electrically contacted with a plurality of different portions of said conductive sheet through openings of said insulating layer.
Claim 14
Dependent Claim
103 words
A semiconductor memory device comprising a semiconductor substrate, a plurality of memory cells formed on said substrate, each of said memory cells including a switch transistor and a storage capacitor coupled to said transistor with its first plate, a second plate of said capacitor being coupled to a predetermined potential, a conductive sheet formed on said semiconductor substrate and forming said second plates of a plurality of said capacitors, and a wiring of highly-conductive material formed on said conductive sheet via an insulating layer and electrically contacted with a plurality of different portions of said conductive sheet through openings of said insulating layer.
Claim 15
Dependent Claim
22 words
The memory device according to claim 11, wherein said conductive sheet includes a layer of a refractory metal or a silicide thereof.
Claim 16
Dependent Claim
13 words
The memory device according to claim 11, wherein said highly-conductive material is aluminium.
References Cited (Backward Citations)
No citation records indexed.
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