EP0156307A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Pipelined processor having dual cache memories
Assignee: FOUR-PHASE SYSTEMS Inc
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Filing: 1985-03-21
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Granted: —
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Expires: 2005-03-21
Abstract
Abstract A pipelined digital computer processor system (10, Figure 1) is provided comprising an instruction prefetch unit (IPU, 2) for prefetching instructions and an arithmetic logic processing unit (ALPU, 4) for executing instructions. The IPU (2) has associated with it a high speed instruction cache (6), and the ALPU (4) has associated with it a high speed operand cache (8). Each cache comprises a data store (84, 94, Figure 3) for storing frequently accessed data, and a tag store (82, 92, Figure 3) for indicating which main memory locations are contained in the respective cache. The IPU and ALPU processing units (2, 4) may access their associated caches independently under most conditions. When the ALPU performs a write operation to main memory, it also updates the corresponding data in the operand cache and, if contained therein, in the instruction cache. The IPU does not write to either cache. Provision is made for clearing the caches on certain conditions when their contents become invalid.
Inventors
- 👤 Richard F. Thompson
- 👤 Daniel J. Disney
- 👤 Swee-Meng Quek
- 👤 Eric C. Westerfeld
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 10:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3812; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F9/3824
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
236 words
A digital processing system for use with a relatively large capacity, slow cycle time main memory unit (30) storing at addressable locations thereof a relatively large number of blocks of information, including instructions and operands, useable in said system, said digital processing system comprising: an instruction prefetch unit (2) for fetching said instructions; an arithmetic logic processing unit (4) for executing said instructions; a relatively low capacity, fast cycle time instruction cache memory unit (6) associated with said instruction prefetch unit for storing at addressable locations thereof a limited number of blocks of said information, said instruction cache memory unit including means responsive to said instruction prefetch unit for determining whether information sought by it is contained therein; and - a relatively low capacity, fast cycle time operand cache memory unit (8) associated with said arithmetic logic unit for storing at addressable locations thereof a limited number of blocks of said information, said operand cache memory unit including means responsive to said arithmetic logic processing unit for determining whether information sought by it is contained therein; whereby the cycle time of said instruction prefetch unit is reduced by the extent to which information sought by it is already present in said instruction cache memory unit, and whereby the cycle time of said arithmetic logic processing unit is reduced by the extent to which information sought by it is already present in said operand cache memory unit.
Claim 2
Dependent Claim
236 words
A digital processing system for use with a relatively large capacity, slow cycle time main memory unit (30) storing at addressable locations thereof a relatively large number of blocks of information, including instructions and operands, useable in said system, said digital processing system comprising: an instruction prefetch unit (2) for fetching said instructions; an arithmetic logic processing unit (4) for executing said instructions; a relatively low capacity, fast cycle time instruction cache memory unit (6) associated with said instruction prefetch unit for storing at addressable locations thereof a limited number of blocks of said information, said instruction cache memory unit including means responsive to said instruction prefetch unit for determining whether information sought by it is contained therein; and - a relatively low capacity, fast cycle time operand cache memory unit (8) associated with said arithmetic logic unit for storing at addressable locations thereof a limited number of blocks of said information, said operand cache memory unit including means responsive to said arithmetic logic processing unit for determining whether information sought by it is contained therein; whereby the cycle time of said instruction prefetch unit is reduced by the extent to which information sought by it is already present in said instruction cache memory unit, and whereby the cycle time of said arithmetic logic processing unit is reduced by the extent to which information sought by it is already present in said operand cache memory unit.
Claim 3
Dependent Claim
226 words
The digital processing system recited in claim 1, wherein said main memory unit stores said information in the form of a plurality of data words each identified by a unique address word; wherein each of said cache memory units comprises: first storage means (84, 94, FIG. 2B) for storing said respective limited number of blocks of information in the form of a limited number of said data words, at least one of said data words in said first storage means being addressable by a low order portion of a unique address word generated by said respective instruction prefetch unit or said arithmetic logic processing unit to fetch said data word, and wherein said determining means comprises: second storage means (82, 92, FIG. 2B) for storing the high order portions of said address words corresponding to said data words stored in said first storage means, said second storage means being addressable by said low order portion of said address word, and means for comparing (86, 96, FIG. 2B) the high order portion of said unique address word with the high order portion stored in said second storage means corresponding to said low order portion of said unique address word, said comparing means providing an indication of whether the data word corresponding to said unique address word is present or not present in said corresponding cache memory unit.
Claim 4
Dependent Claim
32 words
The digital processing system recited in claim 1, wherein said arithmetic logic processing unit comprises means for writing information simultaneously in said main memory unit and in said operand cache memory unit.
Claim 5
Dependent Claim
53 words
The digital processing system recited in claim 3, wherein said arithmetic logic processing unit further comprises: means for determining whether an earlier version of said information being written is contained within said instruction cache memory unit and, if so, for writing the current version of said information in said instruction cache memory unit.
Claim 6
Dependent Claim
81 words
The digital processing system recited in claim 1, wherein said central processing unit further comprises: means for detecting when the contents of either cache memory unit are invalid and for providing a status indication of invalid contents, and means for clearing the contents of a cache memory unit containing invalid data and for reloading said cache memory unit with the appropriate information from said main memory unit, and for causing said detecting means to provide a status indication of valid contents.
References Cited (Backward Citations)
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