EP0155787A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1985-02-28
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Granted: —
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Expires: 2005-02-28
Abstract
Abstract A semiconductor memory device comprises a reset signal generator (RG) for generating a reset signal (⌀ R ) for resetting a bit line pair to an equal potential when a chip selection control signal (C̅S̅) represents a nonselection state of a memory chip. The reset signal has a reset period longer than a predetermined period even when the period of the chip selection control state representing the nonselection state is shorter than the predetermined period, thereby ensuring the reset of the bit line pair and shortening the accessing time.
Inventors
- 👤 Syoichiro Kawashima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 05:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C8/00; G11C8/18; G11C7/00; G11C7/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
94 words
A semiconductor memory device having a selection state and a nonselection state, in response to a control signal, said device comprising a pair of signal lines for transfering complementary signals, and a reset signal generator for generating a first reset signal for resetting said signal lines to an equal potential when said control signal represents said nonselection state of said device, said first reset signal having a reset period longer than a predetermined period even when the time period of the nonselection state represented by said control signal is shorter than said predetermined period.
Claim 2
Dependent Claim
94 words
A semiconductor memory device having a selection state and a nonselection state, in response to a control signal, said device comprising a pair of signal lines for transfering complementary signals, and a reset signal generator for generating a first reset signal for resetting said signal lines to an equal potential when said control signal represents said nonselection state of said device, said first reset signal having a reset period longer than a predetermined period even when the time period of the nonselection state represented by said control signal is shorter than said predetermined period.
Claim 3
Dependent Claim
94 words
A semiconductor memory device as set forth in claim 1, wherein said device further comprises an address buffer circuit for providing complementary address signals on respective complementary address signal lines Which are reset to an equal potential during said nonselection state, and said reset signal generator includes a pulse generating circuit for generating a second reset signal in response to a change of said complementary address signals, said complementary signals being reset by a reset signal having a longer reset period obtained from either said first reset signal or said second reset signal. '
Claim 4
Dependent Claim
34 words
A semiconductor memory device as set forth in claim 2, wherein the pulse width of said second reset signal becomes shorter in accordance with an increase of the time period of said nonselection state.
Claim 5
Dependent Claim
25 words
A semiconductor memory device as set forth in claim 1, 2 or 3, wherein the signal lines of claim 1 are a bit line pair.
Claim 6
Dependent Claim
79 words
A semiconductor memory device as set forth in any preceding claim, wherein said reset signal generator comprises a flip-flop for receiving, at a set terminal, said control signal, and a delay circuit far delaying, by a time necessary for such resetting of the signal lines of claim 1, the output of said flip-flop, the output of said delay circuit being employed to reset said flip-flop, and the output of said flip-flop being used to provide the first reset signal.
Claim 7
Dependent Claim
115 words
A semiconductor memory device, of the kind which can be switched from a selection state to a non-selection state and maintained in the latter state by the application thereto of a control signal pulse, including a pair of signal lines for transferring respective complementary signals, and resetting means actuable, in response to application of the said control signal pulse, to bring about equalisation of the respective potentials of the said signal lines, characterised in that the said resetting means comprise a reset signal generator which operates to ensure that the process of equalisation is continued for a period longer than a predetermined minimum period even if the control signal pulse is shorter than that period.
Claim 8
Dependent Claim
115 words
A semiconductor memory device, of the kind which can be switched from a selection state to a non-selection state and maintained in the latter state by the application thereto of a control signal pulse, including a pair of signal lines for transferring respective complementary signals, and resetting means actuable, in response to application of the said control signal pulse, to bring about equalisation of the respective potentials of the said signal lines, characterised in that the said resetting means comprise a reset signal generator which operates to ensure that the process of equalisation is continued for a period longer than a predetermined minimum period even if the control signal pulse is shorter than that period.
References Cited (Backward Citations)
No citation records indexed.
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