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EP0155041A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

A frequency doubler

Assignee: American Microsystems Holding Corp
•
Filing: 1985-02-27
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Granted: —
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Expires: 2005-02-27
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Abstract

Abstract A unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifier, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers constructed in accordance with the teachings of this invention do not require the use of a phase lock loop, thereby resulting in a substantial simplification of circuit construction. Furthermore, frequency doublers constructed in accordance with this invention utilize a feedback technique which assures that the duty cycle of the output signal will be 50 %, or any other predefined value.

Inventors

  • 👤 Yusuf A. Haque

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 02:25
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/00006; H03K5/156; H03K5/1565

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 109 words
A frequency doubler circuit comprising: an input terminal for receiving an input signal; an output terminal for providing an output signal having a frequency twice the frequency of said input signal; a delay means having an input lead connected to said input terminal and having an output terminal; an exclusive OR gate having a first input lead connected to said input terminal, a second input lead connected to said output lead of said delay means, and an output lead which provides an intermediate signal having twice the frequency of said input signal; and means for adjusting the duty cycle of said intermediate signal to equal a desired duty cycle.
Claim 2
Dependent Claim 109 words
A frequency doubler circuit comprising: an input terminal for receiving an input signal; an output terminal for providing an output signal having a frequency twice the frequency of said input signal; a delay means having an input lead connected to said input terminal and having an output terminal; an exclusive OR gate having a first input lead connected to said input terminal, a second input lead connected to said output lead of said delay means, and an output lead which provides an intermediate signal having twice the frequency of said input signal; and means for adjusting the duty cycle of said intermediate signal to equal a desired duty cycle.
Claim 3
Dependent Claim 80 words
The structure as in Claim 1 wherein said means for adjusting comprises: means responsive to said intermediate signal which provides a ramp voltage to increase in magnitude; means for integrating said output voltage, providing an integrated voltage; means for comparing said ramp voltage and said integrated voltage, thereby providing a logical one output voltage when said ramp voltage is greater than said integrated voltage, and a logical zero output voltage when said ramp voltage is less than said integrated voltage.
Claim 4
Dependent Claim 38 words
The structure as in Claim 2 wherein: said means for integrating is powered by a positive voltage source +Vred and a negative voltage source -Vred such that the duty cycle D of said output signal is defined as:

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