EP0155019A1 — Logic adder circuit

Claim 1

Independent Claim 288 words

A logic full-adder circuit for adding two binary numbers a and b which each consist of n bits, n being a natural number larger than or equal to 2, comprising an inverting OR-gate and an inverting AND-gate for each bit a i , b i of the numbers a and b, where 0≤ i≤ n, said gates receiving the bit signals a i and b i in order to form an inverted OR-signal a i + b i and an inverted AND signal a i .b i , and also comprising a suming circuit for forming a sum signal s i from the bit signals a i and b i and an associated carry signal c i and/or the inverse c i thereof, said full-adder circuit also comprising a carry look-ahead signal circuit for generating a carry look-ahead signal c n + 1 having the significance n + 1 from all inverted OR-signals and AND-signals a i + b i and a i . b., where 0≤i≤ n, characterized in that each summing circuit comprises a logic gate which receives the bit signals a i and b i and the inverted AND-signal a i . b i in order to form a logic signal a i .b i .(a i + b.) on a first output thereof and the inverted logic signal a i .b i . (a i + b.) on a second output thereof, and also comprises electronic switches which connect, under the control of the carry signal c i and/or the inverse c i thereof, either the first output or the second output of the logic gate to a first junction in order to generate an inverted sum signal s i on the first junction.

Claim 2

Dependent Claim 288 words

A logic full-adder circuit for adding two binary numbers a and b which each consist of n bits, n being a natural number larger than or equal to 2, comprising an inverting OR-gate and an inverting AND-gate for each bit a i , b i of the numbers a and b, where 0≤ i≤ n, said gates receiving the bit signals a i and b i in order to form an inverted OR-signal a i + b i and an inverted AND signal a i .b i , and also comprising a suming circuit for forming a sum signal s i from the bit signals a i and b i and an associated carry signal c i and/or the inverse c i thereof, said full-adder circuit also comprising a carry look-ahead signal circuit for generating a carry look-ahead signal c n + 1 having the significance n + 1 from all inverted OR-signals and AND-signals a i + b i and a i . b., where 0≤i≤ n, characterized in that each summing circuit comprises a logic gate which receives the bit signals a i and b i and the inverted AND-signal a i . b i in order to form a logic signal a i .b i .(a i + b.) on a first output thereof and the inverted logic signal a i .b i . (a i + b.) on a second output thereof, and also comprises electronic switches which connect, under the control of the carry signal c i and/or the inverse c i thereof, either the first output or the second output of the logic gate to a first junction in order to generate an inverted sum signal s i on the first junction.

Claim 3

Dependent Claim 110 words

A logic full-adder circuit as claimed in Claim 1, characterized in that the full-adder circuit comprises a carry signal circuit for generating an inverted carry signal c i+1 from the CR-signal a i + b i the NAD-signal a i .b i and the carry signal c i and/or the inverse c i thereof, said carry signal circuit comprising electronic switches which connect, under the control of the carry signal c i and/or the inverse c i thereof, either the output of the inverting OR-gate or the output of the inverting AND-gate to a second junction, the inverted carry signal c i + 1 being generated on said second junction.

Claim 4

Dependent Claim 111 words

A logic full-adder circuit as claimed in Claim 2, which full-adder circuit is constructed with complementary insulated-gate field-effect transistors, characterized in that the electronics switches together comprise four N-channel field-effect transistors, a first and a second transistor thereof connecting the second and the first output, respectively of the said logic gate, to the first junction, the third and the fourth transistor connecting the output of the inverting OR-gate and the output of the inverting AND-gate, respectively, to the second junction, the first and the third transistor being controlled by the carry signal c i and the second and the fourth transistor being controlled by the inverted carry signal c i .

Claim 5

Dependent Claim 37 words

A logic full-adder circuit as claimed in Claim 3, characterized in that P-channel field-effect transistors, which are controlled by the carry signal c i , are connected in parallel with the second and the fourth transistors respectively.

Claim 6

Dependent Claim 46 words

A logic full-adder circuit as claimed in Claim 3, characterized in that two series-connected inverters are connected to the second junction for producing on the outputs thereof a carry signal c i+1 and the inverted carry signal c i+1 having the significance i + 1, respectively.

Claim 7

Dependent Claim 192 words

A logic full-adder circuit as claimed in any one of the Claims 3, 4 and 5, characterized in that the logic gate comprises: a series connection of two P-channel transistors which receive the bit signals a i and b i respectively on their gate electrodes, a further P-channel transistor which is connected in parallel with the two P-channel transistors and whose gate electrode receives the inverted AND-signal a i .b i , a parallel connection of two N-channel transistors which is connected in series with the parallel connection of the P-channel transistors, the gate electrodes of said N-channel transistors receiving the bit signals a i and b i respectively and a further N-channel transistor which is connected in series with the two parallel-connected N-channel transistors and whose gate electrode receives the inverted AND-signal a i . b i , the logic gate also comprising an inverter which is composed of a P- and an N-channel and whose gate electrode is connected to the junction of said P- and N-channel transistors which forms the first output of the logic gate, the output of the inverter forming the second output of the logic gate.

Claim 8

Dependent Claim 128 words

A logic full-adder circuit as claimed in any one of the preceding Claims, characterized in that the carry look-ahead signal circuit comprises a first series connection of transistors, gate electrodes of which receive the AND-signals a i .b i with an ascending significance, the transistor whose gate electrode receives the AND-signal a 0 .b 0 of lowest significance 0 being connected in series with a carry transistor whose gate electrode receives the carry signal c 0 having the significance 0, one transistor being connected in parallel with each section of the series connection of the carry transistor and m further transistors from said first series connection, m assuming any value from 1 to n, the gate electrode of said one transistor receiving the OR-signal a m-1 + m-1

Claim 9

Dependent Claim 48 words

A logic full-adder circuit as claimed in Claim 7, characterized in that the transistors which are connected in series and in parallel in the carry look-ahead signal circuit are N-channel field-effect transistors which are connected in series with a single P-channel field-effect transistor between two power supply terminals.

Logic adder circuit

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