Improved structure of power supply wirings in semiconductor integrated circuit

Claim 2

A semiconductor device comprising a semiconductor substrate, a first circuit section positioned in a center portion of said substrate, a second circuit section provided in the peripheral portion of said substrate, a first power supply wiring layer for supplying a first voltage to said second circuit section and running along a peripheral edge of said substrate, a second power supply wiring layer for supplying said first voltage to said first circuit section and extending on said first circuit section, a third power supply wiring layer for supplying a second voltage to said second circuit section and/or said first circuit section, a MOS type capacitor having a first electrode, a second electrode and a dielectric film between said first and second electrodes, the first electrode being electrically connected to both said first and second power supply wiring layers and said second electrode being electrically connected to said third power supply wiring layer, an insulating layer provided under said first, second and third power supply wiring layers and above said MOS capacitor, and at least one signal line formed on said insulating layer above said MOS capacitor.

Claim 3

A device of Claim 1, in which said first electrode of said MOS type capacitor is an impurity region of one conductivity type formed in a portion of the opposite conductivity type of the substrate.

Claim 4

A device of Claim 1, in which said second electrode of said MOS type capacitor is a polycrystalline silicon plate. 1

Claim 5

A device of Claim 1, in which said first voltage is ground potential, and said second voltage is Vcc potential.

Claim 6

A device of Claim 1, in which said first to third power supply wiring layers and said signal line are made of same conductive material.

Claim 7

A device of Claim 5, in which said material is aluminum.

Claim 8

A semiconductor device comprising a semiconductor substrate, a first power supply wiring layer for supplying a first power supply voltage to circuits at the peripneral portion of said substrate, a second power supply wiring layer for supplying a second power supply voltage to said circuits at said peripheral portion of said substrate, running on the inner side of said first power supply wiring layer and extending substantially in parallel with said first power supply wiring layer, a third power supply wiring layer for supplying said first voltage to circuits at a central portion of said substrate and running on the inner side of said second power supply wiring layer, a first enlarged conductive layer for electrically connecting said first and third power supply wiring layers and positioned under said second power supply wiring layer and having a predetermined area, a second enlarged conductive layer provided under said second power supply wiring layer, an insulating film positioned between said first and second enlarged conductive layers so as to form a capacitor with said first and second enlarged conductive layers, first means for electrically connecting said first and third power supply wiring layers to said first enlarged conductive layer, a second means for electrically connecting said second power supply wiring layer to said second enlarged conductive layer, and signal lines extending on said substrate between said first and third power supply wiring layers and above said first and second enlarged conductive layers.

Claim 9

A semiconductor device comprising a semiconductor substrate, a first power supply wiring layer for supplying a first power supply voltage to circuits at the peripneral portion of said substrate, a second power supply wiring layer for supplying a second power supply voltage to said circuits at said peripheral portion of said substrate, running on the inner side of said first power supply wiring layer and extending substantially in parallel with said first power supply wiring layer, a third power supply wiring layer for supplying said first voltage to circuits at a central portion of said substrate and running on the inner side of said second power supply wiring layer, a first enlarged conductive layer for electrically connecting said first and third power supply wiring layers and positioned under said second power supply wiring layer and having a predetermined area, a second enlarged conductive layer provided under said second power supply wiring layer, an insulating film positioned between said first and second enlarged conductive layers so as to form a capacitor with said first and second enlarged conductive layers, first means for electrically connecting said first and third power supply wiring layers to said first enlarged conductive layer, a second means for electrically connecting said second power supply wiring layer to said second enlarged conductive layer, and signal lines extending on said substrate between said first and third power supply wiring layers and above said first and second enlarged conductive layers.

Claim 10

A device of Claim 7, in which said first enlarged conductive layer is an impurity region of one conductivity type formed in a portion of the opposite conductivity type of said substrate.

Claim 11

A device of Claim 7, in which said second enlarged conductive layer is a polycrystalline silicon plate.

Claim 12

A device of Claim 7, in which said first voltage is ground potential, and said second voltage is Vcc potential.

Claim 13

A device of Claim 7, in which said first to third wiring layers and said signal lines are made of same conductive material and formed by a conductive film deposited on an insulating layer through a same process step.

Claim 14

A semiconductor memory device comprising a semiconductor substrate, a memory array section positioned in a center portion of said substrate, a peripheral circuit section provided in said substrate and abutted against a first side of said memory array section, a wiring forming area positioned in a peripheral portion of said substrate and abutted against a second side of said memory array section, a first power supply wiring layer for supplying a first voltage to said peripheral circuit section and extending on said wiring forming area, a second power supply wiring layer for supplying said first voltage to said memory array section and extending on said memory array section near said second side of said memory array section, a third power supply wiring layer for supplying a second voltage to said peripheral circuit section and/or said memory array section, a MOS type capacitor having a first electrode, a second electrode and a dielectric film between said first and second electrodes, the first electrode being electrically connected to both said first and second power supply wiring layer and said second electrode being electrically connected to said third power supply wiring layer, an insulating layer provided under said first, second and third power supply wiring layers and above said MOS capacitor, and a signal line formed on said insulating layer above said MOS capacitor.

Claim 15

A semiconductor memory device comprising a semiconductor substrate, a memory array section positioned in a center portion of said substrate, a peripheral circuit section provided in said substrate and abutted against a first side of said memory array section, a wiring forming area positioned in a peripheral portion of said substrate and abutted against a second side of said memory array section, a first power supply wiring layer for supplying a first voltage to said peripheral circuit section and extending on said wiring forming area, a second power supply wiring layer for supplying said first voltage to said memory array section and extending on said memory array section near said second side of said memory array section, a third power supply wiring layer for supplying a second voltage to said peripheral circuit section and/or said memory array section, a MOS type capacitor having a first electrode, a second electrode and a dielectric film between said first and second electrodes, the first electrode being electrically connected to both said first and second power supply wiring layer and said second electrode being electrically connected to said third power supply wiring layer, an insulating layer provided under said first, second and third power supply wiring layers and above said MOS capacitor, and a signal line formed on said insulating layer above said MOS capacitor.

Claim 16

A semiconductor memory device comprising a semiconductor substrate, a memory array section provided in said substrate, a peripheral circuit section provided in said substrate, a first power supply wiring layer for supplying a first voltage to said peripheral circuit section formed on said substrate, a second power supply wiring layer for supplying said first voltage to said memory array section formed on said substrate and extending in one direction substantially in parallel with said first power supply wiring layer, a third power supply wiring layer for supplying a second voltage to said peripheral circuit section and/or said memory array section formed on said substrate and extending in said one direction between said first and second power supply wiring layers, a first means for electrically connecting said first and second power supply wiring layers each other, positioned under said third power supply wiring layer and having a predetermined area, a conductive part positioned under said third power supply wiring layer, an insulating film positioned between said first mefns and said conductive part so as to form a capacitor with said first means and said conductive part, a second means for electrically connecting said third power supply wiring layer to said conductive part, and signal lines extending on said substrate between said first and third power supply wiring layers and/cr said second and third power supply wiring layers.

Claim 17

A semiconductor memory device comprising a semiconductor substrate, a memory array section provided in said substrate, a peripheral circuit section provided in said substrate, a first power supply wiring layer for supplying a first voltage to said peripheral circuit section formed on said substrate, a second power supply wiring layer for supplying said first voltage to said memory array section formed on said substrate and extending in one direction substantially in parallel with said first power supply wiring layer, a third power supply wiring layer for supplying a second voltage to said peripheral circuit section and/or said memory array section formed on said substrate and extending in said one direction between said first and second power supply wiring layers, a first means for electrically connecting said first and second power supply wiring layers each other, positioned under said third power supply wiring layer and having a predetermined area, a conductive part positioned under said third power supply wiring layer, an insulating film positioned between said first mefns and said conductive part so as to form a capacitor with said first means and said conductive part, a second means for electrically connecting said third power supply wiring layer to said conductive part, and signal lines extending on said substrate between said first and third power supply wiring layers and/cr said second and third power supply wiring layers.