Logic circuit

Claim 2

A logic circuit comprising: a pair of transistors formed by junction type or Schottky barrier type field effect transistors; a constant current source connected to a common source terminal of said field effect transistors; a pair of load elements respectively connected between each drain terminal of said field effect transistors and a power supply; and a clamp circuit connected between said drain terminals of said field effect transistors.

Claim 3

A logic circuit according to claim 1, wherein said clamp circuit is formed by two diodes connected in parallel between the drain terminals of said field effect transistors and having opposite polarities.

Claim 4

A logic circuit according to claim 1, wherein said clamp circuit is formed by two field effect transistors connected in parallel between the drain terminals of said field effect transistors, and a source and gate of said two field effect transistors are short circuited so as to-form a cathode and the drain of said two field effect transistors is used as an anode, and said two field effect transistors are connected between said drain terminals of said field effect transistors with opposite polarity. 2, or 3,

Claim 5

A logic circuit according to claim 1,)wherein said constant current source is formed by a field effect transistor having a source connected to a gate and a drain connected to said common source terminal.

Claim 6

A differential amplifier circuit comprising: a pair of driver field effect transistors formed by junction type or Schottky barrier gate type field effect transistors; a constant current source connected to a common source terminal of said pair of driver field effect transistors; a pair of load elements respectively connected between each drain terminal of said driver field effect transistors and a power supply; and two clamping diodes connected between the drain terminals of said field effect transistors, and having opposite polarities.

Claim 7

A differential amplifier circuit comprising: a pair of driver field effect transistors formed by junction type or Schottky barrier gate type field effect transistors; a constant current source connected to a common source terminal of said pair of driver field effect transistors; a pair of load elements respectively connected between each drain terminal of said driver field effect transistors and a power supply; and two clamping diodes connected between the drain terminals of said field effect transistors, and having opposite polarities.

Claim 8

A logic circuit comprising first and second differential amplifiers, each of said differential amplifiers comprising a pair of transistors formed by junction type or Schottky barrier type field effect transistors having gate terminals as an input terminal, a constant current electric source connected to a common source terminal of said field effect transistors, a pair of load elements respectively connected between each drain terminal of said field effect transistors and an electric source and two outputs being made from the junction point between said load elements and said drain, and a clamp circuit connected between said drain terminals of said field effect transistors, a first and a second level shift circuits each comprising a first field effect transistor having a gate used as an input, a drain connected to an electric source, a level shift diode connected to a source of said first field effect transistor, a constant current source connected to said level shift diode, and an output terminal connected to a junction point between said level shift diode and said constant current source, an input being applied to an input terminal of said first differential amplifier, a reference voltage being applied to another input terminal of said first differential amplifier, the first and the second output terminals being connected to the input terminal of said level shift circuits, the outputs of said first and second level shift circuits being connected to two input terminals of said second differential amplifier, and the outputs generated from two output terminals of said second differential amplifier.

Claim 9

A logic circuit comprising first and second differential amplifiers, each of said differential amplifiers comprising a pair of transistors formed by junction type or Schottky barrier type field effect transistors having gate terminals as an input terminal, a constant current electric source connected to a common source terminal of said field effect transistors, a pair of load elements respectively connected between each drain terminal of said field effect transistors and an electric source and two outputs being made from the junction point between said load elements and said drain, and a clamp circuit connected between said drain terminals of said field effect transistors, a first and a second level shift circuits each comprising a first field effect transistor having a gate used as an input, a drain connected to an electric source, a level shift diode connected to a source of said first field effect transistor, a constant current source connected to said level shift diode, and an output terminal connected to a junction point between said level shift diode and said constant current source, an input being applied to an input terminal of said first differential amplifier, a reference voltage being applied to another input terminal of said first differential amplifier, the first and the second output terminals being connected to the input terminal of said level shift circuits, the outputs of said first and second level shift circuits being connected to two input terminals of said second differential amplifier, and the outputs generated from two output terminals of said second differential amplifier.