EP0154341B1 — Discrete cosine transform processor

Claim 1

Independent Claim 362 words

A discrete cosine transform calculation processor for calculating the transform of a sequence of N digital data points where N = 2" and n is an integer greater than two, comprising arithmetic addition/subtraction and multiplication units, characterized in that it is organized in providing four successive calculation stages each assigned to a single operation and together constituting a processor module (1) controlled by a programmed store (80), wherein said stages comprise - for the first stage, referred to as module input, a first arithmetic addition/subtraction unit (10) with two input buses receiving the data points to be processed in successive pairs and an output bus (SI) delivering the results, - for the second stage, a second arithmetic addition/subtraction unit (20) with two input buses and an output bus (Sll), first and second. addressable storage registers (24A, 24B) each associated with a respective one of the input buses of said second arithmetic addition/subtraction unit, and multiplexer circuits (22A, 23A, 22B, 23B) selectively loading said first and second registers from the output bus (SI) of the first stage or from an internal bus, referred to as loop back bus (S'A, S'B) of the module and feeding each input bus of said second arithmetic addition/subtraction unit from the output bus of the first stage or the associated register; - for the third stage, a multiplication unit (30) having an output bus and two input buses respectively connected to an associated adressable store (32) holding sine and cosine function values and to the output bus (SII) of said second stage; - and for the fourth stage, referred to as module output, a third arithmetic addition/subtraction unit (40) having two input buses and an output bus (SIV) to which said loopback bus (S'A, S'B) is connected to load selectively said first and second registers, third and fourth addressable storage registers (43A, 43B) each associated with one of said input buses of said third arithmetic addition/ subtraction unit and loaded selectively from the output bus of the third stage, and multiplexer circuits (42A, 42B) selectively feeding each input bus of said third arithmetic addition/subtraction unit from the output bus (Sill) of the third stage or the associated register.

Claim 2

Dependent Claim 362 words

A discrete cosine transform calculation processor for calculating the transform of a sequence of N digital data points where N = 2" and n is an integer greater than two, comprising arithmetic addition/subtraction and multiplication units, characterized in that it is organized in providing four successive calculation stages each assigned to a single operation and together constituting a processor module (1) controlled by a programmed store (80), wherein said stages comprise - for the first stage, referred to as module input, a first arithmetic addition/subtraction unit (10) with two input buses receiving the data points to be processed in successive pairs and an output bus (SI) delivering the results, - for the second stage, a second arithmetic addition/subtraction unit (20) with two input buses and an output bus (Sll), first and second. addressable storage registers (24A, 24B) each associated with a respective one of the input buses of said second arithmetic addition/subtraction unit, and multiplexer circuits (22A, 23A, 22B, 23B) selectively loading said first and second registers from the output bus (SI) of the first stage or from an internal bus, referred to as loop back bus (S'A, S'B) of the module and feeding each input bus of said second arithmetic addition/subtraction unit from the output bus of the first stage or the associated register; - for the third stage, a multiplication unit (30) having an output bus and two input buses respectively connected to an associated adressable store (32) holding sine and cosine function values and to the output bus (SII) of said second stage; - and for the fourth stage, referred to as module output, a third arithmetic addition/subtraction unit (40) having two input buses and an output bus (SIV) to which said loopback bus (S'A, S'B) is connected to load selectively said first and second registers, third and fourth addressable storage registers (43A, 43B) each associated with one of said input buses of said third arithmetic addition/ subtraction unit and loaded selectively from the output bus of the third stage, and multiplexer circuits (42A, 42B) selectively feeding each input bus of said third arithmetic addition/subtraction unit from the output bus (Sill) of the third stage or the associated register.

Claim 3

Dependent Claim 176 words

A processor according to claim 1, for calculating the two-dimensional transform of blocks of N x N digital picture elements of a picture signal, characterized in that it further comprises a set of three stores (50, 60, 70), first, second and third stores, individually controlled in read and write modes by said programmed store (80) and associated with said module, and comprising, for each store, an incoming and outgoing word multiplexer (52, 62, 72) and a respective store addressing multiplexer (53, 63, 73), both controlled by said programmed store (80) to connect sequentially said first store (50), which has two access ports, in read mode and then the second store (60), which also has two access ports (10A, 10B) in read mode to both input buses of the first stage of said module (1), whereas said second store (60) in write mode and then the third store in write mode, are connected successively for the same sequences, to the output bus (SIV) of the output stage of the module (1) to transfer the module result words.

Claim 4

Dependent Claim 75 words

A processor according to claim 2, characterized in that it further comprises a controller circuit (90) for storing the picture element in blocks of N x N coefficients resulting from the transform of each block, which is serially connected to said first store (50) for loading successive picture element blocks in this store, and to said third store (70) for unloading blocks of N x N word resulting from the module and constituting said coefficients.

Discrete cosine transform processor

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