EP0154340B1 — Inverse discrete cosine transform processor

Claim 1

Independent Claim 295 words

A processor for calculating the discrete inverse cosine transform, comprising arithmetical additional and subtraction units and multiplication units for the calculation of the transform of a sequence of N digital data, called coefficients, where N = 2" and n is an integer greater than 2, characterized in that it is organized in four successive calculation stages each assigned to a single and equal operation and together constituting a processor module which is controlled by a programmed storage (80), - that the first stage, called input module stage, comprises an arithmetical multiplication unit (10) connected to an associated addressable storage (13) holding sine and cosine function values, and an input multiplexer (12) selectively connecting an input bus (1E) of the module receiving said coefficients, or an internal bus (lB) of the module called loopback bus, to said multiplication unit, said multiplication unit delivering the successive products obtained on a stage output bus (SI), - that the second, third and fourth stages each comprise an arithmetic addition and subtraction unit (20, 30, 40) having two input busses and a stage output bus (SII, Slll, SIV), the output bus of the fourth stage constituting the output bus of the module, two addressable storage registers (23A, 23B, 33A, 33B, 43A, 43B), loaded from the output bus of the stage immediately preceding the concerned stage, and two stage input multiplexers (22A, 22B, 32A, 32B, 42A, 42B) which each connect selectively the output bus of said immediately preceding stage or the output bus of one of the registers of the concerned stage to one of the input busses of the addition and substraction unit of this stage, and that said loopback bus (1B) is connected to the output bus of one of the addressable storage registers (43A) of the fourth stage.

Claim 2

Dependent Claim 295 words

A processor for calculating the discrete inverse cosine transform, comprising arithmetical additional and subtraction units and multiplication units for the calculation of the transform of a sequence of N digital data, called coefficients, where N = 2" and n is an integer greater than 2, characterized in that it is organized in four successive calculation stages each assigned to a single and equal operation and together constituting a processor module which is controlled by a programmed storage (80), - that the first stage, called input module stage, comprises an arithmetical multiplication unit (10) connected to an associated addressable storage (13) holding sine and cosine function values, and an input multiplexer (12) selectively connecting an input bus (1E) of the module receiving said coefficients, or an internal bus (lB) of the module called loopback bus, to said multiplication unit, said multiplication unit delivering the successive products obtained on a stage output bus (SI), - that the second, third and fourth stages each comprise an arithmetic addition and subtraction unit (20, 30, 40) having two input busses and a stage output bus (SII, Slll, SIV), the output bus of the fourth stage constituting the output bus of the module, two addressable storage registers (23A, 23B, 33A, 33B, 43A, 43B), loaded from the output bus of the stage immediately preceding the concerned stage, and two stage input multiplexers (22A, 22B, 32A, 32B, 42A, 42B) which each connect selectively the output bus of said immediately preceding stage or the output bus of one of the registers of the concerned stage to one of the input busses of the addition and substraction unit of this stage, and that said loopback bus (1B) is connected to the output bus of one of the addressable storage registers (43A) of the fourth stage.

Claim 3

Dependent Claim 241 words

A processor according to claim 1, applied to the calculation of the two-dimensional transform of matrix blocks of N x N coefficience corresponding to the direct transform of matrix blocks of N x N digital picture elements of a picture signal, characterized in that it further comprises a set of three addressable storages (50, 60, 70), referred to as first, second and third storages, associated to said processor module (1) and individually controlled in read and write modes by said programmed storage (80), and for each one of said first, second and third storages, two multiplexers, the first one referred to as input and output word transfer multiplexer of the concerned storage and the other referred to as storage addressing multiplexer, both controlled simultaneously by said programmed storage, the input and output word transfer multiplexers ensuring in two processing sequences for the entire set of three storages the selective connection of said first storage (50) in the read mode, than the second storage (60) in read mode to the input bus (1E) of said module (1) while during these same sequences, the second storage (60) in the write mode and then the third storage (70) also in the write mode are connected to the output bus S4 of said module (1) and the addressing multiplexers transmitting to said storages during these same sequences the successive read and write addresses of each one of the storages supplied by the programmes storage (80).

Claim 4

Dependent Claim 87 words

A processor according to claim 2, characterized in that it further comprises a main controller circuit (90) adapted to store said coefficience and said corresponding elaborated picture elements in blocks of N x N, connected during a sequence called initialisation to said first storage (50) two loads, each of the successive blocks N x N coefficience onto this first storage, and during a final sequence connected to said third storage (70) to unload the block of N x N reconstituted picture elements from this third storage (70).

Inverse discrete cosine transform processor

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag