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EP0154082A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Gate turn-off thyristor

Assignee: Toshiba Corp
•
Filing: 1984-11-14
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Granted: —
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Expires: 2004-11-14
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Abstract

Abstract A gate tum-off thyristor has a first emitter layer (31) having a P + P- emitter structure which is in contact with an anode electrode (35) and a second emitter layer (34) having an N-type mutli-emitter structure which is in contact with cathode electrodes (36). To reduce power dissipation in the tum-off process, the first emitter layer (31) mainly consists of low impurity concentration regions (39), and each high impurity concentration region (38) has a substantially uniform width and surrounds a low impurity concentration region (39) of the first emitter layer immediately below one of the emitter strips (34, to 34 n ) of the second emitter layer.

Inventors

  • 👤 Takashi Patent Division Shinohe
  • 👤 Masayuki Patent Division Asaka

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 16:21
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/60; H10D62/00; H10D62/10; H10D62/13; H10D62/141; H10D62/142

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 227 words
A gate turn-off thyristor comprising: a first emitter layer (31) of a first conductivity type; a first base layer (32) of a second conductivity type formed on said first emitter layer; a second base layer (33) of the first conductivity type formed on said first base layer; a second emitter layer (34) of the second conductivity type formed on said second base layer, said first emitter'layer consisting of high impurity concentration regions (38) and low impurity concentration regions (39), said second emitter layer being divided into a plurality of nearly rectangular emitter strips (34 1 to 34 n ) on said second base layer (33), and PN-junctions being formed between said emitter strips and said second base layer; an anode electrode (35) which is in contact with said first emitter layer; cathode electrodes (36 1 to 36 n ) which are in contact with said second emitter layer; and a gate electrode (37) which is in contact with said second base layer excluding said PN-junctions, characterized in that each of said high impurity concentration regions (38) of said first emitter layer (31) is formed to have a substantially uniform width and to surround at least part of the periphery of one of said low impurity concentration regions (39) having a nearly rectangular shape and formed within regions of said first emitter layer just below said emitter strips.
Claim 2
Dependent Claim 227 words
A gate turn-off thyristor comprising: a first emitter layer (31) of a first conductivity type; a first base layer (32) of a second conductivity type formed on said first emitter layer; a second base layer (33) of the first conductivity type formed on said first base layer; a second emitter layer (34) of the second conductivity type formed on said second base layer, said first emitter'layer consisting of high impurity concentration regions (38) and low impurity concentration regions (39), said second emitter layer being divided into a plurality of nearly rectangular emitter strips (34 1 to 34 n ) on said second base layer (33), and PN-junctions being formed between said emitter strips and said second base layer; an anode electrode (35) which is in contact with said first emitter layer; cathode electrodes (36 1 to 36 n ) which are in contact with said second emitter layer; and a gate electrode (37) which is in contact with said second base layer excluding said PN-junctions, characterized in that each of said high impurity concentration regions (38) of said first emitter layer (31) is formed to have a substantially uniform width and to surround at least part of the periphery of one of said low impurity concentration regions (39) having a nearly rectangular shape and formed within regions of said first emitter layer just below said emitter strips.
Claim 3
Dependent Claim 64 words
A gate turn-off thyristor according to claim 1, characterized in that, assuming that the length of the short side of said low impurity concentration region (39) of said first emitter layer (31) is X P E and the width of said high impurity concentration region (38) of said first emitter layer (31) is X p+, X P E and XpE are related as follows:
Claim 4
Dependent Claim 26 words
A gate turn-off thyristor according to claim 1, characterized in that said high impurity concentration region (38) of said first emitter layer (31) is annularly formed.
Claim 5
Dependent Claim 31 words
A gate turn-off thyristor according to claim 1, characterized in that said high impurity concentration regions (38) of said first emitter layer (31) are integrally formed with the substantially uniform width.
Claim 6
Dependent Claim 26 words
A gate turn-off thyristor according to claim 1, characterized in that said first conductivity type is P type and said second conductivity type is N type.

References Cited (Backward Citations)

EP0066850A2 Cited

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