Gate turn-off thyristor
Abstract
Abstract A gate tum-off thyristor has a first emitter layer (31) having a P + P- emitter structure which is in contact with an anode electrode (35) and a second emitter layer (34) having an N-type mutli-emitter structure which is in contact with cathode electrodes (36). To reduce power dissipation in the tum-off process, the first emitter layer (31) mainly consists of low impurity concentration regions (39), and each high impurity concentration region (38) has a substantially uniform width and surrounds a low impurity concentration region (39) of the first emitter layer immediately below one of the emitter strips (34, to 34 n ) of the second emitter layer.
Inventors
- 👤 Takashi Patent Division Shinohe
- 👤 Masayuki Patent Division Asaka
Bibliographic Details
Claims Analysis
Total Claims: 6References Cited (Backward Citations)
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