Circuit for generating test signals for in-circuit digital testing

Claim 2

Apparatus adapted for use with a central processor [10] for the in-circuit testing during a test cycle of the electrical properties of components interconnected at electrical nodes in a circuit under test [26], the components being responsive to nodal test vector signals having first, second, and disconnect logic states where a test vector comprises the logic states occurring at any given time in the test cycle in nodal test signals involved in the test of a component, the apparatus comprising: (1) a test vector processor [18] responsive to said central processor [10] for controlling the generation of said nodal test vector signals during the test cycle; and (2) a plurality of digital test signal means [22] responsive to said vector processor [18], (a) each said test means [22] capable of generating a nodal test signal to the circuit under test, and (b) each said test means [22] including circuit means [58, 60, 62, 64, 65] for storing test signal generating data and, responsive to said stored test signal generating data, for controlling the generation of the logic state of a nodal test signal where the logic state is controlled to (i) keep the same logic state as the previous logic state, (ii) toggle to the opposite state as the previous logic state, or (iii) to assume either a logic zero or a logic one state regardless of the previous logic state.

Claim 3

The apparatus of claim 1 wherein said circuit means also stores enable data for controlling the application of the nodal test signal to the circuit under test, each said test signal means further including a driver means [55] responsive to the nodal test signal from said circuit means and said stored enable data to output the nodal test signal to the circuit under test when enabled by said enable data.

Claim 4

The apparatus of claim 2 wherein said vector processor controls the generation of the nodal test signals by generating to each said digital test signal means a sequence of ordered memory addresses, each said circuit means including random access memory [58, 60] for storing said test signal generating data and said enable data, and where N digital test signal means, responsive to stored keep-toggle test signal generating data and said sequence of memory addresses, generate N nodal test signals having 2N unique test vectors where each test vector comprises an N-bit digital code formed from the logic states occurring in the N digital nodal test signals.

Claim 5

The apparatus of claim 1 wherein said vector processor comprises a high-speed microcoded processor [30] having a random access program memory [32] for storing microcoded program instructions which are loaded from the central processor [10] prior to a test cycle.

Claim 6

Apparatus adapted for use with a central processor [10] for the in-circuit testing during a test cycle of the electrical properties of components interconnected at electrical nodes in a circuit under test [26], the components being responsive to nodal test signals having first, second, and disconnect logic states which states occur in clock intervals, the apparatus comprising: (1) a programmable sequence controller [18] responsive to the central processor [10] for controlling the generation of said nodal test signals during the test cycle, said programmable sequence controller including a high-speed microcoded processor [30]; (2) a plurality of digital test signal generators [22], each responsive to said central processor and said controller, and each capable of generating a nodal test signal, each said generator including, (a) a memory means [58] for storing data to generate a nodal test signal and enabling data to control the outputting of a nodal test signal to the circuit under test, (b) a circuit means [62, 64] responsive to said memory means [58] for generating a flip-flop output signal [83] which either, (i) remains unchanged from the previous logic state, (ii) toggles to the opposite logic state as its previous logic state, (iii) assumes a logic zero state regardless of its previous logic state, or (iv) assumes a logic one state regardless of its previous logic state; and, (c) a driver means [55] responsive to said flip-flop output signal and said test signal enabling data for outputting a nodal test signal to the circuit under test when enabled by said enabling data.

Claim 7

Apparatus adapted for use with a central processor [10] for the in-circuit testing during a test cycle of the electrical properties of components interconnected at electrical nodes in a circuit under test [26], the components being responsive to nodal test signals having first, second, and disconnect logic states which states occur in clock intervals, the apparatus comprising: (1) a programmable sequence controller [18] responsive to the central processor [10] for controlling the generation of said nodal test signals during the test cycle, said programmable sequence controller including a high-speed microcoded processor [30]; (2) a plurality of digital test signal generators [22], each responsive to said central processor and said controller, and each capable of generating a nodal test signal, each said generator including, (a) a memory means [58] for storing data to generate a nodal test signal and enabling data to control the outputting of a nodal test signal to the circuit under test, (b) a circuit means [62, 64] responsive to said memory means [58] for generating a flip-flop output signal [83] which either, (i) remains unchanged from the previous logic state, (ii) toggles to the opposite logic state as its previous logic state, (iii) assumes a logic zero state regardless of its previous logic state, or (iv) assumes a logic one state regardless of its previous logic state; and, (c) a driver means [55] responsive to said flip-flop output signal and said test signal enabling data for outputting a nodal test signal to the circuit under test when enabled by said enabling data.