Viterbi decoder with the pipeline processing function

Claim 2

A Viterbi decoder with a pipeline processing function for decoding a received code sequence transferred from an encoder, characterised by: correlation determining means (11 and 12a through 12d) for calculating correlation between a received code sequence (11101111) and each of a plurality of predetermined code sequences of known allowable transitions; and a selecting means (13a through 13d and 14) operatively receiving said correlations for selecting one of said predetermined code sequences as the maximum likelihood transition, the selected one of said predetermined code sequences having the maximum correlation among said correlations, a decoded code sequence being obtained from said selected one of said predetermined code sequences, wherein said correlation determining means comprises: a plurality of new correlation determining means (31 through 34) each for determining a new correlation based on newly received code sequence and an already calculated correlation between the already received code sequence and one of said predetermined code sequences; and comparing means (41a) for comparing, simultaneously with the determination of the new correlations, already calculated correlations between the already received code sequence and said predetermined code sequences, so as to output a path selecting data; said selecting means selecting, in response to said selecting data, one of said predetermined code sequences as the maximum likelihood sequence with respect to the code sequence generated by the encoder.

Claim 3

A Viterbi decoder with a pipeline processing function for decoding a received code sequence transferred from an encoder, characterised by: a clock signal generator (43) for generating a clock signal having predetermined clock cycle periods; a first correlation determining circuit (11) for obtaining, during each of said clock cycle periods, a plurality of first correlations (bm) between a unit {(1, 1), (1, 0), (1, 1), or (1, I)} of a received code sequence and a plurality of fixed units {(0, 0), (1, 1), (1, 0), (0, 1)} of predetermined code sequences, each fixed unit of said predetermined code sequences corresponding to a predetermined path from one state to a subsequent state of said encoder when said encoder generates one of said predetermined code sequences; a plurality of second correlation determining circuits (12a through 12d) for obtaining, during each of said clock cycle periods, a plurality of second correlations (pm), each of said second correlations being determined based on one of said first correlations corresponding to an allowable. transition and at least two of already calculated second correlations corresponding to allowable transitions, said already calculated second correlations calculated during a clock cycle period just before the current clock cycle period; and a first selecting circuit (14) for selecting one of said predetermined code sequences, said selected code sequence having the maximum correlation among the resultant second correlations, a decoded code sequence being obtained from said selected code sequence; wherein each of said second correlation determining circuits (12a through 12d) comprises: a comparing circuit (41a) for comparing, during each of said clock cycle periods, said already calculated second correlations so as to output path selecting data, said path selecting data corresponding to the maximum correlation among said already calculated second correlations, said path selecting data being supplied from said comparing circuit to said first selecting circuit, said first selecting circuit selecting one of said predetermined code sequences in response to said path selecting data; a plurality of adding circuits (31 through 34) each for adding, during each of said clock cycle periods, one of said first correlations (bm) to one of said already calculated second correlations so as to output a new second correlation; a plurality of second selecting circuits (37 and 38) each for selecting, in response to said path selecting data output from said comparing means, one of said new second correlations, the selected new second correlation having the maximum correlation among said new second correlations applied to each of said second selecting circuits; and a plurality of updating circuits (39 and 40) for updating said already calculated second correlations by said selected new second correlations during a period subsequent to the period when said already calculated second correlations are compared simultaneous with the additions of said first correlations to said already calculated second correlations.

Claim 4

A Viterbi decoder with a pipeline processing function for decoding a received code sequence transferred from an encoder, characterised by: a clock signal generator (43) for generating a clock signal having predetermined clock cycle periods; a first correlation determining circuit (11) for obtaining, during each of said clock cycle periods, a plurality of first correlations (bm) between a unit {(1, 1), (1, 0), (1, 1), or (1, I)} of a received code sequence and a plurality of fixed units {(0, 0), (1, 1), (1, 0), (0, 1)} of predetermined code sequences, each fixed unit of said predetermined code sequences corresponding to a predetermined path from one state to a subsequent state of said encoder when said encoder generates one of said predetermined code sequences; a plurality of second correlation determining circuits (12a through 12d) for obtaining, during each of said clock cycle periods, a plurality of second correlations (pm), each of said second correlations being determined based on one of said first correlations corresponding to an allowable. transition and at least two of already calculated second correlations corresponding to allowable transitions, said already calculated second correlations calculated during a clock cycle period just before the current clock cycle period; and a first selecting circuit (14) for selecting one of said predetermined code sequences, said selected code sequence having the maximum correlation among the resultant second correlations, a decoded code sequence being obtained from said selected code sequence; wherein each of said second correlation determining circuits (12a through 12d) comprises: a comparing circuit (41a) for comparing, during each of said clock cycle periods, said already calculated second correlations so as to output path selecting data, said path selecting data corresponding to the maximum correlation among said already calculated second correlations, said path selecting data being supplied from said comparing circuit to said first selecting circuit, said first selecting circuit selecting one of said predetermined code sequences in response to said path selecting data; a plurality of adding circuits (31 through 34) each for adding, during each of said clock cycle periods, one of said first correlations (bm) to one of said already calculated second correlations so as to output a new second correlation; a plurality of second selecting circuits (37 and 38) each for selecting, in response to said path selecting data output from said comparing means, one of said new second correlations, the selected new second correlation having the maximum correlation among said new second correlations applied to each of said second selecting circuits; and a plurality of updating circuits (39 and 40) for updating said already calculated second correlations by said selected new second correlations during a period subsequent to the period when said already calculated second correlations are compared simultaneous with the additions of said first correlations to said already calculated second correlations.

Claim 5

A Viterbi decoder as set forth in claim 2, wherein said unit of a received code sequence is a received pair of symbols; said fixed units of said predetermined code sequences are four pairs of symbols (0, 0), (1, 1), (1, 0), and (0, 1); said first correlations are branch metrics; and said first correlation determining circuit (11) comprises first branch metric calculating unit (lla) for calculating a first branch metric equal to a Hamming distance between said received pair of symbols and the first one of said fixed units (0, 0), a second branch metric calculating unit (llb) for calculating a second branch metric equal to a Hamming distance between said received pair of symbols and the second one of said fixed units (1, 1), a third branch metric calculating unit (llc) for calculating a third branch metric equal to a Hamming distance between said received pair of symbols and the third one of said fixed units (1, 0), and a fourth branch metric calculating unit for calculating a fourth branch metric equal to a Hamming distance between said received pair of symbols and the fourth one of said fixed units (0, 1).

Claim 6

A Viterbi decoder as set forth in claim 3, wherein said second correlations are path metrics each representing a cumulative correlation between said received code sequence and one of said predetermined code sequences, the smaller the path metric, the larger the correlation.

Claim 7

A Viterbi decoder as set forth in claim 4, comprising four of said second correlation determining circuits respectively corresponding to four states "00", "10", "01", and "11" of the encoder, each of said second correlation determining circuits operatively receiving two branch metrics from two of said branch metric calculating circuits corresponding to the allowable transitions to the state corresponding to said second correlation determining circuit under consideration, and also receiving two already calculated path metrics from two of said second correlation determining circuits corresponding to the allowable transitions to the state corresponding to said second correlation determining circuit under consideration.

Claim 8

A Viterbi decoder as set forth in claim 5, wherein said updating circuits are metric memories connected through said second selecting circuits to said adding circuits, each of said metric memories operatively storing a new path metric selected by said second selecting circuits in response to a clock signal generated by said clock signal generator, said adding circuits and said comparing circuit operatively calculate said new path metric during a clock cycle period just before a clock cycle period when said new path metrics are stored in said metric memories.