EP0152651A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Circuit for generating the programming voltage for an erasable read-only memory
Assignee: Koninklijke Philips NV
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Filing: 1984-12-19
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Granted: —
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Expires: 2004-12-19
Abstract
Abstract In order to prevent an excessively fast rise of the programming voltage for an (E)EPROM, a stage is inserted which on the one hand prevents voltage losses and which on the other realizes the required large time constant of the voltage rise in spite of the use of small capacitances.
Inventors
- 👤 Cornelis Dietwin Hartgring
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 15:10
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
123 words
A circuit for generating the programming voltage for an erasable programmable read-only memory (EPROM, EEPROM), comprising a voltage source which is connected, via a charging resistor, to the memory section to be programmed which is bridged by a (stray) capacitance, characterized in that in a circuit in parallel with a charging circuit of the memory section which is bridged by the (stray) capacitance, there is connected a first transistor whose control electrode is controlled by the voltage on a capacitor which is connected, in series with the conductance path of a second transistor, in parallel with the capacitance of said charging circuit, said first and second transistor being connected as a current mirror which amplifies current from the second to the first transistor.
Claim 2
Dependent Claim
123 words
A circuit for generating the programming voltage for an erasable programmable read-only memory (EPROM, EEPROM), comprising a voltage source which is connected, via a charging resistor, to the memory section to be programmed which is bridged by a (stray) capacitance, characterized in that in a circuit in parallel with a charging circuit of the memory section which is bridged by the (stray) capacitance, there is connected a first transistor whose control electrode is controlled by the voltage on a capacitor which is connected, in series with the conductance path of a second transistor, in parallel with the capacitance of said charging circuit, said first and second transistor being connected as a current mirror which amplifies current from the second to the first transistor.
Claim 3
Dependent Claim
52 words
A circuit as claimed in Claim 1, characterized in that between said second transistor and the capacitor there is provided a third transistor which is connected as a voltage follower and whose gate is connected to said capacitor whilst its voltage follower electrode is connected to the gate of said first transistor.
Claim 4
Dependent Claim
47 words
A circuit as claimed in Claim 1, in which the transistors are constructed as field-effect transistors, characterized in that the width/length ratio of the channel of the first transistor is substantially larger, for example at least an order of magnitude larger, than that of the second transistor.
Claim 5
Dependent Claim
40 words
A circuit as claimed in Claim 2 or 3, in which the third transistor is also constructed as a field-effect transistor, characterized in that the width/length ratio of the channel of the third transistor exceeds that of the second transistor.
Claim 6
Dependent Claim
47 words
A circuit as claimed in Claim 1, in which the transistors are constructed as field-effect transistors, characterized inthat in parallel with the first transistor there are connected one or more further transistors which can be switched on as desired and whose channel width/length ratios are mutually different.
References Cited (Backward Citations)
No citation records indexed.
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