EP0152624A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device having a polycristalline silicon-active region.
Assignee: Sony Corp
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Filing: 1984-12-24
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Granted: —
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Expires: 2004-12-24
Abstract
Abstract @ A thin film semiconductor device with a polycrystalline silicon film forming an active channel region, a source region and a drain region, is encapsulated in a passivation layer which also serves as a source of free hydrogen. Migration of hydrogen into the active region improves the effective carrier mobility, the threshold voltage and the gate voltage of the device by reducing carrier trap density thereof. The passivation layer is activated during annealing to drive hydrogen through porous or transmissive layers of the device of the active region. Effective mobilities of up to 100 cm 2 /V sec can be achieved in the preferred construction. The semiconductor device can be fabricated in the form of IC chips.
Inventors
- 👤 Hisao Hayashi
- 👤 Hisayoshi Yamoto
- 👤 Chiaki Sakai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 04:52
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/94; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D62/00; H10D62/40; H10D86/00; H10D86/01; H10D88/00; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/66; H10P14/668; H10P14/6681; H10P14/6682; H10W; H10W74/00; H10W74/40; H10W74/43
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
117 words
A semiconductor device comprising: a substrate; a polycrystalline silicon layer forming an active region, a source region and a drain region, said polycrystalline silicon layer being deposited on said substrate; a gate electrode formed on said polycrystalline silicon layer above said active region, with an insulating layer interposed between said polycrystalline silicon layer and said gate electrode; electrodes, one connected to each of said source region and said drain region; a passivation layer deposited over said polycrystalline silicon layer, said gate electrode and said electrodes, said passivation layer containing hydrogen free to migrate during annealing into said polycrystalline silicon layer and fill charge carrier traps in said polycrystalline silicon layer and preventing said trap-filling hydrogen from escaping.
Claim 2
Dependent Claim
117 words
A semiconductor device comprising: a substrate; a polycrystalline silicon layer forming an active region, a source region and a drain region, said polycrystalline silicon layer being deposited on said substrate; a gate electrode formed on said polycrystalline silicon layer above said active region, with an insulating layer interposed between said polycrystalline silicon layer and said gate electrode; electrodes, one connected to each of said source region and said drain region; a passivation layer deposited over said polycrystalline silicon layer, said gate electrode and said electrodes, said passivation layer containing hydrogen free to migrate during annealing into said polycrystalline silicon layer and fill charge carrier traps in said polycrystalline silicon layer and preventing said trap-filling hydrogen from escaping.
Claim 3
Dependent Claim
32 words
The semiconductor device as set forth in claim 1, wherein said passivation layer is a silicon nitride layer deposited by plasma chemical vapor deposition process using a mixture of hydrogenated reagent gases.
Claim 4
Dependent Claim
21 words
The semiconductor device as set forth in claim 2, wherein said reagent gases are silane (SiH 4 ) and ammonia (NH3).
Claim 5
Dependent Claim
20 words
The semiconductor device as set forth in claim 1, wherein said polycrystalline silicon layer is between 100Å and 750Å thick.
Claim 6
Dependent Claim
20 words
The semiconductor device as set forth in 0 0 claim 4, wherein said polysilicon layer is 100A to 600A thick.
Claim 7
Dependent Claim
20 words
The semiconductor device as set forth in 0 0 claim 5, wherein said polysilicon layer is 200A to 500A thick.
Claim 8
Dependent Claim
37 words
The semiconductor device as set forth in claim 4, wherein said passivation layer comprises a silicon nitride layer deposited by plasma chemical vapor deposition using a mixture of silane (SiH 4 ) and ammonia (NH 3 ).
Claim 9
Dependent Claim
136 words
A process for fabricating a semiconductor device comprising the steps of: depositing a polycrystalline silicon layer on a substrate; forming a gate electrode and a gate insulating layer, the latter lying between said polycrystalline silicon layer and said gate electrode; deposing selected areas of said polycrystalline silicon layer to form a source region, a drain region and an active region, the last lying beneath said gate insulating layer; connecting electrodes to said source region and to said drain region; depositing a hydrogenated passivation layer over the entire surface of the semiconductor device; and annealing the semiconductor device for exciting the hydrogen in said passivation layer to migrate into said active region of said polycrystalline silicon layer and adhere to charge carrier traps in said polycrystalline silicon layer, thereby reducing the trap density in said active region.
Claim 10
Dependent Claim
136 words
A process for fabricating a semiconductor device comprising the steps of: depositing a polycrystalline silicon layer on a substrate; forming a gate electrode and a gate insulating layer, the latter lying between said polycrystalline silicon layer and said gate electrode; deposing selected areas of said polycrystalline silicon layer to form a source region, a drain region and an active region, the last lying beneath said gate insulating layer; connecting electrodes to said source region and to said drain region; depositing a hydrogenated passivation layer over the entire surface of the semiconductor device; and annealing the semiconductor device for exciting the hydrogen in said passivation layer to migrate into said active region of said polycrystalline silicon layer and adhere to charge carrier traps in said polycrystalline silicon layer, thereby reducing the trap density in said active region.
Claim 11
Dependent Claim
26 words
The process as set forth in claim 8, wherein said passivation layer is deposited by plasma chemical vapor deposition employing a mixture of hydrogenated gaseous reagents.
Claim 12
Dependent Claim
22 words
The process as set forth in claim 9, wherein said gaseous reagents are silane (SiH 4 ) and ammonia (NH 3 ).
Claim 13
Dependent Claim
25 words
The process as set forth in claim 10, wherein said polycrystalline silicon layer is deposited to a thickness in the range of 100A to 750A.
Claim 14
Dependent Claim
18 words
The process as set forth in claim 11, wherein o o said thickness range is 100A to 600A.
Claim 15
Dependent Claim
18 words
The process as set forth in claim 12, wherein ° ° said thickness range is 200A to 500A.
Claim 16
Dependent Claim
24 words
The process as set forth in claim 8, wherein said annealing step is performed at a temperature in the range of 300°C to 500°C.
Claim 17
Dependent Claim
80 words
An IC circuit comprising: a plurality of semiconductor devices, each having a plurality of operating regions including an active region; a passivation layer extending over said semiconductor devices, said passivation layer containing hydrogen which is free to migrate into said active regions and adhere to charge carrier traps in said active regions, thereby reducing the trap density therein; and means defining a path in each semiconductor device through which hydrogen may migrate from said passivation layer to said active region.
Claim 18
Dependent Claim
80 words
An IC circuit comprising: a plurality of semiconductor devices, each having a plurality of operating regions including an active region; a passivation layer extending over said semiconductor devices, said passivation layer containing hydrogen which is free to migrate into said active regions and adhere to charge carrier traps in said active regions, thereby reducing the trap density therein; and means defining a path in each semiconductor device through which hydrogen may migrate from said passivation layer to said active region.
Claim 19
Dependent Claim
33 words
The IC chip as set forth in claim 15, wherein said path is defined through one or more insulating layers, through which at least one of said operating regions opposes said passivation layer.
Claim 20
Dependent Claim
24 words
The IC chip as set forth in claim 16, wherein said passivation layer comprises a silicon nitride layer formed by plasma chemical vapor deposition.
Claim 21
Dependent Claim
22 words
The IC chip as set forth in claim 17, wherein said silicon nitride layer is deposited upon reaction of two hydrogenated reagents.
Claim 22
Dependent Claim
22 words
The IC chip as set forth in claim 18, wherein said reagents are silane (SiH 4 ) and ammonia (NH 3 ).
Claim 23
Dependent Claim
22 words
The IC chip as set forth in claim 19, wherein 0 said polycrystalline silicon layer is between 100A and 0 750A thick.
Claim 24
Dependent Claim
21 words
The IC chip as set forth in claim 20, wherein said polycrystalline silicon layer is between 200A and 0 500A thick.
References Cited (Backward Citations)
No citation records indexed.
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