Gate array integrated circuit using schottky-barrier FETs

Abstract

Abstract A gate array integrated circuit in which gate cells (11) are each composed of a DCFL circuit using Schottky-barrier FETs. A plurality of basic gate cells is arrayed in one direction to form a basic cell array (10), and such basic cell arrays are arranged parallel to each other. VDD lines (12) and GND lines (13) are provided to apply an operating voltage to the basic gate cells. In order to stably operate the gate array integrated circuit of DCFL structure in which the logic swing and noise margin are small, the VDD lines (12) and the GND lines (13) are arranged perpendicular to each other such that the number of the basic gate cells (11) which are connected to each of the VDD lines is larger than that of the basic gate cells (11) which are connected, to each of the GND lines (13). According to this layout, the potential difference (voltage drop) developed in the GND lines by operation current is reduced.

Inventors

• 👤 Yasuo C/O Patent Division Ikawa
• 👤 Nobuyuki C/O Patent Division Toyoda
• 👤 Katsue C/O Patent Division Kanazawa
• 👤 Takamaro C/O Patent Division Mizoguchi
• 👤 Akimichi C/O Patent Division Hojo

Bibliographic Details