High speed and high accuracy analog to digital converter

Claim 2

An analog to digital converter for converting an analog input signal to a digital representation having n bits which include a plurality of more significant bits and a plurality of less significant bits, the converter comprising: flash analog to digital converter means for converting the analog input signal to an approximate digital representation wherein the flash converter includes a plurality of series connected resistors, each resistor having a comparator associated therewith for comparing the analog signal with the voltage at the associated resistor, and encoder means for encoding the output of the comparators to provide the more significant bits of the digital representation; and a register having n bit positions for storing an n-bit digital representation, said bit positions including positions for storing the plurality of more significant bits provided by the flash converter means, and positions corresponding to the plurality of less significant bits; comparison means for comparing the analog value of the n-bit digital representation stored in the register and the analog input signal and for providing an output in accordance with said comparison; and means responsive to the comparison means for successively testing each less significant bit position of the register and changing the bit values of the bit positions as required so that the analog value of the n-bit digital representation substantially equals the analog input signal wherein the bits stored in the register are an n-bit digital representation of the analog input signal.

Claim 3

The converter of Claim 1 further comprising means for subtracting a predetermined amount from the more significant bits prior to storing the more significant bits into the register wherein the amount subtracted is a function of the expected accuracy of the flash converter means.

Claim 4

The converter of Claim 2 further comprising means responsive to the comparison means for incrementing selected bit positions of the more significant bits stored in the register if the analog value of the digital representation is lower than the analog input signal.

Claim 5

The converter of Claim 1 further comprising means for adding a predetermined amount to the more significant bits prior to storing the more significant bits into the register wherein the amount added is a function of the expected accuracy of the flash converter means.

Claim 6

The converter of Claim 4 further comprising means responsive to the comparison means for decrementing selected bit positions of the more significant bits stored in the register if the analog value of the digital representation is higher than the analog input signal.

Claim 7

A high speed analog-to-digital converter for converting an analog input signal to a digital representation having a plurality of bits which include a first plurality of more significant bits and a second plurality of less significant bits, said converter comprising: parallel analog-to-digital converter means for converting the analog signal to an approximate digital representation which includes the first plurality of more significant bits, said converter means having means for converting at least two of the first plurality of bits from the analog input signal in parallel; and successive approximation analog to digital converter means responsive to the parallel analog to digital converter means, for completing the conversion of the analog signal to a digital representation which includes the less significant digits, wherein the less significant digits are provided by a successive approximation analog to digital technique.

Claim 8

A high speed analog-to-digital converter for converting an analog input signal to a digital representation having a plurality of bits which include a first plurality of more significant bits and a second plurality of less significant bits, said converter comprising: parallel analog-to-digital converter means for converting the analog signal to an approximate digital representation which includes the first plurality of more significant bits, said converter means having means for converting at least two of the first plurality of bits from the analog input signal in parallel; and successive approximation analog to digital converter means responsive to the parallel analog to digital converter means, for completing the conversion of the analog signal to a digital representation which includes the less significant digits, wherein the less significant digits are provided by a successive approximation analog to digital technique.

Claim 9

The converter of Claim 6 wherein the successive approximation digital to analog converter means includes: a register having a first plurality of bit positions for storing the first plurality of more significant bits and a second plurality of bit positions for storing the second plurality of less significant bits; comparison means for comparing the analog value of the digital representation stored in the successive approximation register to the analog input signal; and control means responsive to the comparison means for successively storing a test value into each of the second plurality of less significant bit positions of the successive approximation register and resetting each of the second plurality of less significant bit positions as required in accordance with said comparison.

Claim 10

The converter of Claim 6 further comprising means for modifying the approximate digital representation computed by the parallel analog to digital converter means by a first predetermined value to provide a first plurality of more significant test bits, said successive approximation analog to digital converter means further comprising means for successively comparing the first plurality of more significant test bits to the analog input signal and modifying the first plurality of more significant test bits by a second predetermined value as necessary until the analog value of the modified first plurality of more significant bits differs by less than a third predetermined value from the analog input signal.

Claim 11

The converter of Claim 8 wherein the successesive approximation analog to digital converter means for modifying the first plurality of more significant bits includes a counter.

Claim 12

The converter of Claim 6 wherein the parallel analog to digital converter means comprises a reference voltage, a plurality of series connected equal resistance resistors coupled'to the reference voltage wherein the reference voltage is equally divided over the resistors; a plurality of comparators, each comparator having an input connected to a resistor and an input connected to the analog input signal to compare the voltage of the analog input signal to the portion of the reference voltage appearing at the associated resistor; and encoder means for encoding the outputs of the comparators to an approximate digital representation of the analog input signal.

Claim 13

A high speed analog to digital converter for converting an analog input signal to a digital representation having a plurality of bits which include a first plurality of more significant bits and a second plurality of less significant bits, said converter comprising: = -a successive approximation register having a first plurality of more significant bit positions and a second plurality of less significant bit positions for storing the first and second plurality of bits, respectively; parallel analog to digital converter means for converting the analog signal to an approximate digital representation which includes a first plurality of more significant bits, wherein at least two of the first plurality of bits are computed in parallel; means for subtracting a predetermined quantity corresponding to the maximum possible error of the parallel analog to digital converter means from the plurality of more significant bits computed by the parallel analog to digital converter means and storing the resultant difference in the first plurality of bit positions of the successive approximation register; comparison means for comparing the analog value of the digital numbers stored in the successive approximation register to the analog input signal and providing a comparison signal in accordance with the comparison; and control means responsive to the comparison means for successively incrementing the first plurality of bits stored in the successive approximation register if the analog value of the number stored in the successive approximation register is less than analog input signal, said comparison occurring a predetermined number of times and for storing a test value into each of the less significant bit positions of the successive approximation register and successively testing each of the less significant bit positions and setting the value of the tested bit position as required in accordance with the comparison of the analog value of the representation stored in the successive approximation register to the analog input signal.

Claim 14

A high speed analog to digital converter for converting an analog input signal to a digital representation having a plurality of bits which include a first plurality of more significant bits and a second plurality of less significant bits, said converter comprising: = -a successive approximation register having a first plurality of more significant bit positions and a second plurality of less significant bit positions for storing the first and second plurality of bits, respectively; parallel analog to digital converter means for converting the analog signal to an approximate digital representation which includes a first plurality of more significant bits, wherein at least two of the first plurality of bits are computed in parallel; means for subtracting a predetermined quantity corresponding to the maximum possible error of the parallel analog to digital converter means from the plurality of more significant bits computed by the parallel analog to digital converter means and storing the resultant difference in the first plurality of bit positions of the successive approximation register; comparison means for comparing the analog value of the digital numbers stored in the successive approximation register to the analog input signal and providing a comparison signal in accordance with the comparison; and control means responsive to the comparison means for successively incrementing the first plurality of bits stored in the successive approximation register if the analog value of the number stored in the successive approximation register is less than analog input signal, said comparison occurring a predetermined number of times and for storing a test value into each of the less significant bit positions of the successive approximation register and successively testing each of the less significant bit positions and setting the value of the tested bit position as required in accordance with the comparison of the analog value of the representation stored in the successive approximation register to the analog input signal.