EP0151418A1
Expired / Lapsed
EP
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Pulse width modulation inverter system
Assignee: Hitachi Ltd
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Filing: 1985-01-18
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Granted: —
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Expires: 2005-01-18
Abstract
Abstract A PWM inverter system for converting DC power to AC power comprises an output voltage setting circuit (12) for generating a pattern of output voltage value corresponding to a speed command value, an oscillator (13) for generating a pulse train having a frequency proportional to the speed command value, a frequency division circuit (14) for dividing the frequency of the pulse train produced by the oscillator to produce interrupt pulses, a pulse interval measuring circuit (15) for measuring a pulse interval between predetermined ones of the interrupt pulses supplied from the frequency division circuit, an arithmetic unit (17) responding to the input of the interrupt pulses from the frequency division circuit to produce a timing signal corresponding to the timing at which said interrupt pulse is inputted and updata data associated with current operating phase relative to a fundamental wave, to thereby produce pulse width data corresponding to the result of multiplication of a value associated with the output voltage value supplied from the output voltage setting circuit, a value associated with the pulse interval supplied from the pulse interval measuring circuit and a value associated with the operating phase relative to said fundamental wave, a pulse width conversion circuit (19) supplied with the pulse width data from the arithmetic unit for producing a width pulse train conforming to the pulse width data at every timing signal supplied from the arithmetic unit, and a waveform processing circuit (20) supplied with the width pulse train from the pulse width conversion circuit and the timing signal from the arithmetic unit to produce sequentially phase output pulse trains.
Inventors
- 👤 Hiroshi Fujii
- 👤 Hideyuki Shimonabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 19:14
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5387; H02M7/53871; H02M7/53873
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
265 words
A PWM inverter system comprising: an output voltage setting circuit (12) for generating a pattern of output voltage value corresponding to a speed command value; an oscillator (13) for generating a pulse train having a frequency proportional to said speed command value; a frequency division circuit (14) for dividing the frequency of said pulse train produced by said oscillator to produce interrupt pulses; a pulse interval measuring circuit (15) for measuring a pulse interval between predetermined ones of said interrupt pulses supplied from said frequency division circuit; an arithmetic unit (17) responding to the input of said interrupt pulses from said frequency division circuit (14) to produce a timing signal corresponding to the timing at which said interrupt pulse is inputted and update data associated with current operating phase relative to a fundamental wave, to thereby produce pulse width data corresponding to the result of multiplication of a value associated with the output voltage value supplied from said output voltage setting circuit (12), a value associated with the pulse interval supplied from said pulse interval measuring circuit (15) and a value associated with said operating phase relative to said fundamental wave (5); a pulse width conversion circuit (19) supplied with said pulse width data from said arithmetic unit (17) for producing a width pulse train conforming to said pulse width data at every timing signal supplied from said arithmetic unit; and a waveform processing circuit (20) supplied with said width pulse train from said pulse width conversion circuit (19) and said timing signal from said arithmetic unit (17) to produce sequentially phase output pulse trains.
Claim 2
Dependent Claim
265 words
A PWM inverter system comprising: an output voltage setting circuit (12) for generating a pattern of output voltage value corresponding to a speed command value; an oscillator (13) for generating a pulse train having a frequency proportional to said speed command value; a frequency division circuit (14) for dividing the frequency of said pulse train produced by said oscillator to produce interrupt pulses; a pulse interval measuring circuit (15) for measuring a pulse interval between predetermined ones of said interrupt pulses supplied from said frequency division circuit; an arithmetic unit (17) responding to the input of said interrupt pulses from said frequency division circuit (14) to produce a timing signal corresponding to the timing at which said interrupt pulse is inputted and update data associated with current operating phase relative to a fundamental wave, to thereby produce pulse width data corresponding to the result of multiplication of a value associated with the output voltage value supplied from said output voltage setting circuit (12), a value associated with the pulse interval supplied from said pulse interval measuring circuit (15) and a value associated with said operating phase relative to said fundamental wave (5); a pulse width conversion circuit (19) supplied with said pulse width data from said arithmetic unit (17) for producing a width pulse train conforming to said pulse width data at every timing signal supplied from said arithmetic unit; and a waveform processing circuit (20) supplied with said width pulse train from said pulse width conversion circuit (19) and said timing signal from said arithmetic unit (17) to produce sequentially phase output pulse trains.
Claim 3
Dependent Claim
22 words
A PWM inverter system according to claim 1, wherein said arithmetic unit (17) produces the pulse width data prepared in accordance with
Claim 4
Dependent Claim
75 words
A PWM inverter syste according to claim 1, wherein said pulse interval measuring circuit (15) measures the pulse interval at every other one of said interrupt pulses, and said arithmetic unit (17) performs arithmetic operations at every input of the interrupt pulse alternately in accordance with and where V represents the output voltage value, Tc represents the pulse interval, wt represents the operating phase relative to the fundamental wave and K represents a proportional constant.
Claim 5
Dependent Claim
105 words
A PWM inverter system according to claim 1, wherein said arithmetic unit (17) responds to every input of the interrupt pulse for outputting a command signal and a timing signal constituted by a value inverting data signal, said pulse width converting circuit (19) responds to the command signal from said arithmetic unit (17) for outputting the width pulse train conforming to the pulse width data supplied from said arithmetic unit, and said waveform processing circuit (20) is supplied with the width pulse train from said pulse width conversion circuit and the data signal from said arithmetic unit for producing sequentially the phase output pulse trains.
Claim 6
Dependent Claim
46 words
A PWM inverter system according to claim 4, where- ing said pulse width conversion circuit (19) responds to the command signal supplied from said arithmetic unit (17) for inverting the output signal during a period corresponding to the pulse width data supplied from said arithmetic unit.
Claim 7
Dependent Claim
49 words
A PWM inverter system according to claim 5, wherein said pulse width conversion circuit (19) responds to the command signal supplied from said arithmetic unit (17) for maintaining the output signal at a state Lo during a period corresponding to the pulse width data supplied from said arithmetic unit.
Claim 8
Dependent Claim
105 words
A PWM inverter system according to claim 3, wherein said arithmetic unit (17) responds to every input of the interrupt pulse for outputting a command signal and a timing signal constituted by a value inverting data singal, said pulse width converting circuit (19) responds to the command signal from said arithmetic unit (17) for outputting the width pulse train conforming to the pulse width data supplied from said arithmetic unit, and said waveform processing circuit (20) is supplied with the width pulse train from said pulse width conversion circuit and the data signal from said arithmetic unit for producing sequentially the phase output pulse trains.
Claim 9
Dependent Claim
45 words
A PWM inverter system according to claim 7, wherein said pulse width conversion circuit (19) responds to the command signal supplied from said arithmetic unit (17) for inverting the output signal during a period corresponding to the pulse width data supplied from said arithmetic unit.
Claim 10
Dependent Claim
49 words
A PWM inverter system according to claim 8, wherein said pulse width conversion circuit (19) responds to the command signal supplied from said arithmetic unit (17) for maintaining the output signal at a state Lo during a period corresponding to the pulse width data supplied from said arithmetic unit.
Claim 11
Dependent Claim
52 words
A PWM inverter system according to claim 8, wherein said waveform processing circuit (20) produces sequentially inverted phase output pulse upon every completion of the inputting of the width pulse of said width pulse train outputted from said pulse width conversion circuit (19) during a period corresponding to the pulse width data.
Claim 12
Dependent Claim
49 words
A PWM inverter system according to claim 9, wherein said waveform processing circuit (20) produces sequentailly the phase output pulse trains maintaining the state of the data signal supplied from said arithmetic unit (17), when the width pulse train signal supplied from said pulse width conversion circuit rises up.
Claim 13
Dependent Claim
283 words
A PWM inverter system for converting DC power to AC power, comprising: an output voltage setting circuit (12) for generating a pattern of output voltage value corresponding to a speed command value; an oscillator (13) for generating a pulse train having a frequency proportional to said speed command value; a frequency division circuit (14) for dividing the frequency of said pulse train produced by said oscillator to produce interrupt pulses; a pulse interval measuring circuit (15) for measuring a pulse interval between predetermined ones of said interrupt pulses supplied from said frequency division circuit; an arithmetic unit (17) responding to the input of said interrupt pulses from said frequency division circuit to produce a timing signal corresponding to the timing at which said interrupt pulse is inputted update data associated with current operating phase relative to a fundamental wave as well as data associated with the frequency dividing ratio corresponding to said speed command value and the pulse interval, and produce pulse width data corresponding to the result of multiplication of a value associated with the output voltage value supplied from said output voltage setting circuit, a value associated with the pulse interval supplied from said pulse interval measuring circuit and a value associated with said operating phase relative to said fundamental wave; a pulse width conversion circuit (19) supplied with said pulse width data from said arithmetic unit for producing a width pulse train conforming to said pulse width data at every timing signal supplied from said arithmetic unit; and a waveform processing circuit (20) supplied with said width pulse train from said pulse width conversion circuit and said timing signal from said arithmetic unit to produce sequentially phase output pulse trains.
Claim 14
Dependent Claim
283 words
A PWM inverter system for converting DC power to AC power, comprising: an output voltage setting circuit (12) for generating a pattern of output voltage value corresponding to a speed command value; an oscillator (13) for generating a pulse train having a frequency proportional to said speed command value; a frequency division circuit (14) for dividing the frequency of said pulse train produced by said oscillator to produce interrupt pulses; a pulse interval measuring circuit (15) for measuring a pulse interval between predetermined ones of said interrupt pulses supplied from said frequency division circuit; an arithmetic unit (17) responding to the input of said interrupt pulses from said frequency division circuit to produce a timing signal corresponding to the timing at which said interrupt pulse is inputted update data associated with current operating phase relative to a fundamental wave as well as data associated with the frequency dividing ratio corresponding to said speed command value and the pulse interval, and produce pulse width data corresponding to the result of multiplication of a value associated with the output voltage value supplied from said output voltage setting circuit, a value associated with the pulse interval supplied from said pulse interval measuring circuit and a value associated with said operating phase relative to said fundamental wave; a pulse width conversion circuit (19) supplied with said pulse width data from said arithmetic unit for producing a width pulse train conforming to said pulse width data at every timing signal supplied from said arithmetic unit; and a waveform processing circuit (20) supplied with said width pulse train from said pulse width conversion circuit and said timing signal from said arithmetic unit to produce sequentially phase output pulse trains.
Claim 15
Dependent Claim
46 words
A PWM inverter system according to claim 12, wherein said pulse interval measuring circuit (15) measures the pulse interval at every other one of said interrupt pulses, and said arithmetic unit performs arithmetic operations at every input of the interrupt pulse alternately in accordance with and
Claim 16
Dependent Claim
34 words
A PWM inverter system according to claim 12, wherein said arithmetic unit (17) updates the data concerning the frequency dividing ratio and the pulse interval when a predetermined speed command value has been attained.
Claim 17
Dependent Claim
47 words
A PWM inverter system according to claim 12, wherein said arithmetic unit (17) updates the data concerning the frequency division ratio and the pulse interval when a predetermined speed command value has been attained and when the operating phase relative to the fundamental wave has reached 0°.
Claim 18
Dependent Claim
32 words
A PWM inverter system according to claim 14, wherein a plurality of the speed command values for updating the data of the frequency dividing ratio and the pulse interval are previously prepared.
Claim 19
Dependent Claim
64 words
A PWM inverter system according to claim 16, wherein said arithmetic unit (17) updates the data concerning the frequency dividing ratio and the pulse interval when a given one of said plural preset speed command values has been attained and when the operating phase relative to the fundamental wave has attained a phase position determined by an integral multiple of 60° starting from 0°.
Claim 20
Dependent Claim
155 words
A PWM inverter system according to claim 13, wherein said arithmetic unit (17) produces as a timing signal a command signal and a data signal for inverting the instantaneous value every time the interrupt pulse is inputted, and updates the data concerning the frequency dividing ratio and the pulse interval when one of the plural preset speed command values has been attained and when the operating phase relative to the fundamental wave has reached 0°; said pulse width converting circuit (19) responds to the command signal from said arithmetic unit for outputting a width pulse signal constituted by the width pulse train conforming to the pulse width data supplied from said arithmetic unit; and said waveform processing circuit (20) is supplied with the width pulse signal constituted by the width pulse train produced from said pulse width conversion circuit and the data signal from said arithmetic unit for producing sequentially the phase output pulse trains.
Claim 21
Dependent Claim
93 words
A PWM inverter system according to claim 18, wherein said pulse width conversion circuit responds to the command signal supplied from said arithmetic unit (17) for maintaining the width pulse signal at the state Lo during a period corresponding to the pulse width data supplied from said arithmetic unit, and said waveform processing circuit (20) produces sequentially phase output pulse trains maintaining the state of the data signal supplied from said arithmetic unit upon rising of the width pulse signal constituted by the width pulse train supplied from said pulse width conversion circuit.
Claim 22
Dependent Claim
73 words
A PWM inverter system according to claim 19, for obtaining a three-phase power, said arithmetic unit (17) performs arithmetic processings upon every input of said interrupt pulse alternately in accordance with and for a first phase, and in accordance with and for a second phase, where V represents the output voltage value, Tc represents the pulse interval, wt represents the operating phase relative to the fundamental wave, and K represents a proportional constant.
References Cited (Backward Citations)
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