EP0150910A2
Expired / Lapsed
EP
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Digital image frame processor
Assignee: Northrop Grumman Guidance and Electronics Co Inc
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Filing: 1985-01-04
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Granted: —
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Expires: 2005-01-04
Abstract
Abstract @ A frame processor for processing digitized image information includes a memory for storing a two-dimensional array of pixels, logic circuits for controlling the writing and reading of Information into the memory, an arithmetic and logic unit having two inputs, one of which is coupled to the output of the memory, and a microprocessor for controlling operation of the arithmetic and logic unit and the logic circuits for controlling reading and writing.
Inventors
- 👤 David R. Wojcik
- 👤 Thomas W. Studwell
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 05:00
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/60; G06T1/20
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
70 words
A frame processor for processing digitized image information comprising: a. a memory for storing a two-dimensional array of pixels; b. means for controlling the writing and reading of information into said memory; c. an ALU having two inputs, one of said inputs coupled to the output of said memory; and d. a microprocessor for controlling operation of said arithmetic and logic unit and said means for controlling reading and writing.
Claim 2
Dependent Claim
70 words
A frame processor for processing digitized image information comprising: a. a memory for storing a two-dimensional array of pixels; b. means for controlling the writing and reading of information into said memory; c. an ALU having two inputs, one of said inputs coupled to the output of said memory; and d. a microprocessor for controlling operation of said arithmetic and logic unit and said means for controlling reading and writing.
Claim 3
Dependent Claim
34 words
Apparatus according to claim 1, wherein said frame processor has at least two input buses and further including a multiplexer for selecting which of said buses is coupled as the input for said memory.
Claim 4
Dependent Claim
26 words
Apparatus according to claim 2, and further including a second multiplexer for selecting one of said buses as the second input to said arithmetic logic unit.
Claim 5
Dependent Claim
56 words
Apparatus according to claim 3, wherein at least one output bus is provided and further including a third multiplexer for selecting any one of a plurality of outputs from within said frame processor including the output of said memory, the output of said ALU and one of said input buses as the output for said bus.
Claim 6
Dependent Claim
35 words
Apparatus according to claim 4, and further incuding means for carrying out an image intensity transformation in said frame processor, said image information transformation output being provided as another selectable output to said third multiplexer.
Claim 7
Dependent Claim
52 words
Apparatus according to claim 5, and further including a fourth multiplexer between said ALU and said image intensity transformation means, permitting selection of one of the output of said ALU the first input to said ALU and the second input to said ALU as the input to said image intensity transformation means.
Claim 8
Dependent Claim
17 words
Apparatus according to claim 6 wherein at least one of said buses is a bidirectional input/output bus.
Claim 9
Dependent Claim
57 words
Apparatus according to claim 7, wherein each frame processor includes a system input bus, a bidirectional A bus, a bidirectional B bus, and a system output bus, said bidirectional buses and system output buses each having a multiplexer to select between the system input bus, the memory output, the ALU output and the image intensity transformation output.
Claim 10
Dependent Claim
24 words
Apparatus according to claim B, and further including a direct memory access bus into said frame processor for providing address control and data signals.
Claim 11
Dependent Claim
49 words
Apparatus according to claim 9, wherein said image intensity transformation means comprises a random access memory, the inputs of which are coupled to the memory addresses, and the outputs of which are the data at those addresses, the memory programmed according to address value to provide an intensity transformation.
Claim 12
Dependent Claim
70 words
Apparatus according to claim 10, wherein said- direct memory access includes an address bus adapted to be coupled through said fourth multiplexer as the address information to said image intensity transformation memory and said direct memory access data bus is coupled to the data lines of said memory whereby information can be remotely read into and out of said memory to change the intensity transformation function from a remote location.
Claim 13
Dependent Claim
38 words
Apparatus according to claim 11, wherein said direct memory access address bus is coupled to said means for controlling reading and writing to said frame memory whereby said frame memory can be remotely addressed and information read therefrom.
Claim 14
Dependent Claim
35 words
Apparatus according to claim 12, wherein said means for reading and writing comprise an X address generator and an Y address generator, said X address generator adapted to be preset to a desired starting address.
Claim 15
Dependent Claim
20 words
Apparatus according to claim 13, and further including means for the controlling the direction of incrementation of said X address.
Claim 16
Dependent Claim
22 words
Apparatus according to claim 13 wherein said X address generator includes inputs for selecting between lines of 512, 1024 and 2048 pixels.
Claim 17
Dependent Claim
40 words
Apparatus according to claim 15 wherein said X address generator comprises: a) a counter generating the first N bits of the address; and b) a programmable logic array generating the one, two or three most significant bits of the address.
References Cited (Backward Citations)
No citation records indexed.
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