EP0150767A2 — Program controlled bus arbitration for a distribu…

Claim 1

Independent Claim 248 words

In a data processing system having a bus (26) including data, address and control lines, a processor (30) connected to said bus and exerting master control thereover, a plurality of requesting devices (10, 76, 50) connected to said bus, each being operative to assert a bus request signal for use of said bus and to use said bus in response to receiving a bus grant signal, hardware controlled bus arbiter means (34) including a plurality of input lines (90) for receiving bus request signals (BRO-BR4) from said requesting devices, a plurality of output (100) lines respectively connected to different ones of said requesting units for asserting first bus grant signals (BGO-BG4), and arbiting means (82, 83) responsive to a single highest priority bus request signal on one of said input lines for asserting a bus grant signal on the one of said output lines connected to the one of said requesting devices from which said single bus request signal originated, said arbiting means being further.operative in response to a plurality of simultaneous bus request signals on plural ones of said input lines for asserting a single bus grant signal on one of said output lines in accordance with a predetermined priority, characterized by software controlled, selectively- actuated control means (85) responsive to program defined signals (DO-D7) for asserting second bus grant signals on a mutually exclusive basis relative to said first bus grant signals, to thereby allow program control of use of said bus by said requesting devices.

Claim 2

Dependent Claim 248 words

In a data processing system having a bus (26) including data, address and control lines, a processor (30) connected to said bus and exerting master control thereover, a plurality of requesting devices (10, 76, 50) connected to said bus, each being operative to assert a bus request signal for use of said bus and to use said bus in response to receiving a bus grant signal, hardware controlled bus arbiter means (34) including a plurality of input lines (90) for receiving bus request signals (BRO-BR4) from said requesting devices, a plurality of output (100) lines respectively connected to different ones of said requesting units for asserting first bus grant signals (BGO-BG4), and arbiting means (82, 83) responsive to a single highest priority bus request signal on one of said input lines for asserting a bus grant signal on the one of said output lines connected to the one of said requesting devices from which said single bus request signal originated, said arbiting means being further.operative in response to a plurality of simultaneous bus request signals on plural ones of said input lines for asserting a single bus grant signal on one of said output lines in accordance with a predetermined priority, characterized by software controlled, selectively- actuated control means (85) responsive to program defined signals (DO-D7) for asserting second bus grant signals on a mutually exclusive basis relative to said first bus grant signals, to thereby allow program control of use of said bus by said requesting devices.

Claim 3

Dependent Claim 65 words

The combination of claim 1 wherein said control means comprises: storage means for storing said program defined signals, a control register responsive to said program defined signals for providing said second bus grant signals, said control register and said storage means being connected to said bus; said processor being operative to control transferring said program defined signals from said storage means to said control register.

Claim 4

Dependent Claim 31 words

The combination of claim 1 wherein said control means comprises means responsive to one of said program defined signals for disabling said arbiting means from asserting said first bus grant signals.

Claim 5

Dependent Claim 53 words

The combination of claim 1 comprising: a second bus connected to said first bus; selectively operated switch means for controlling the transfer of data between said first bus and said second bus; and means in said control means responsive to one of said program defined signals for controlling operation of said switch means.

Claim 6

Dependent Claim 29 words

The combination of claim 1 wherein said control means comprises means responsive to one of said program defined signals for masking said arbiting means from said bus request signals.

Claim 7

Dependent Claim 188 words

In a distributed array processing system including a host system for initiating execution of problem programs, first storage means for storing array operands, an arithmetic processor (AP) for processing array operands, and a data transfer controller (DTC) for transferring array operands between said AP and said first storage means, the improvement comprising: a process control unit (PCU) for executing problem programs and directing the operation of said data transfer controller and said arithmetic unit; a first bus connected to said PCU; a second storage means connected to said first bus for storing said problem programs and control operands; a selectively disabled bus arbiter connected to said first bus and said PCU for controlling usage of said first bus when enabled; a second bus connected between said first storage means, said AP and said DTC, selectively operable switch means connected between said first and second buses for electrically connecting and isolating said buses, and normally disabled control means connected to said first bus, said arbiter and said switch means and being responsive to said control operands for enabling said control means, disabling said arbiter and operating said switch means.

Claim 8

Dependent Claim 188 words

In a distributed array processing system including a host system for initiating execution of problem programs, first storage means for storing array operands, an arithmetic processor (AP) for processing array operands, and a data transfer controller (DTC) for transferring array operands between said AP and said first storage means, the improvement comprising: a process control unit (PCU) for executing problem programs and directing the operation of said data transfer controller and said arithmetic unit; a first bus connected to said PCU; a second storage means connected to said first bus for storing said problem programs and control operands; a selectively disabled bus arbiter connected to said first bus and said PCU for controlling usage of said first bus when enabled; a second bus connected between said first storage means, said AP and said DTC, selectively operable switch means connected between said first and second buses for electrically connecting and isolating said buses, and normally disabled control means connected to said first bus, said arbiter and said switch means and being responsive to said control operands for enabling said control means, disabling said arbiter and operating said switch means.

Claim 9

Dependent Claim 51 words

The combination of claim 6 wherein: said control means comprises a means for receiving said operands and generating a first set of bus grant signals for controlling usage of said bus when said arbiter is disabled; said arbiter being operative when enabled to generate a second set of bus grant signals.

Claim 10

Dependent Claim 53 words

The combination of claim 6 wherein: each of said control operands comprises a plurality of bit signals, said control means being responsive to one of said bit signals to operate said switch means, whereby said DTC can transfer data over said second bus concurrently with said PCU transferring-different data over said first bus.

Program controlled bus arbitration for a distributed array processing system

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