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EP0150592A2
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Time-slot addressed multipler device
Assignee: TE Connectivity Corp
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Filing: 1984-12-13
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Granted: —
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Expires: 2004-12-13
Abstract
Abstract A time-slot addressed, system keyed multiplex device is taught. Briefly stated, a ribbon cable (48) provided a power (V cc ) and ground lead (GND) and a clock (78) and data signal lead (80). A microcomputer or master controller (46) then communicates over the ribbon cable with a plurality of intelligent connectors (52). Each connector is provided with a unique address (A3, A4, A5, A6, A7, A8) such that by counting (U3, U4) the number of clock pulses provided by the master controller, the logic package in the intelligent connector recognizes the appropriate time-slot for a response (194) or command signal (192). A single one-pulse command is then presented by the master controller on the data bus which is then received by the logic circuitry followed by a time period on the data bus when the logic package may send to the master controller a single bit of data. In this manner of command and response, various devices such as relays may be turned on or off with their conditions presented to the master controller.
Inventors
- 👤 Paul Singtse Chang
- 👤 Edward Camp Dowling
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 23:06
CPC Classifications
G; G08; G08C; G08C15/00; G08C15/06; G08C15/12; G05; G05B; G05B2219/00; G05B2219/20; G05B2219/21; G05B2219/21037; G05B2219/25; G05B2219/25051; G05B2219/25315; G05B2219/25321; G05B2219/25324
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
280 words
A time-slot addressed, system keyed multiplex device, comprising: a master controller (46); a timing signal bus (108) having a continuous series of timing signal pulses (48) thereon, said bus being in communication with the master controller; a data bus (108) in communication with the master controller; at least one logic package (52) having a unique address code (A3, A4, A5, A6, A7, A8), said package in communication with said timing signal bus and said data bus, and being characterized by: a timing circuit (U2, U5/B) having an input connected to receive a timing signal (MCK) on said timing signal bus and producing an output signal representative of the number of timing signal pulses (U3, U4); comparator means (U5/A, U6) adapted to compare said output signal of said timing circuit with a predetermined address code thereby producing a comparator means output signal (Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7) when said output signal of said timing circuit is equal to the address code; an input line (RE1, RE2, RE3, REIn for receiving a logical input command signal from an external device and/or load (32); an output line (Cl, C2, C3, C4) for providing a logical output command signal to an external device and/or load; and logic gating means (U8, U10, U12, U13) adapted to receive said comparator means output signal such that upon receiving said comparator means output signal said logical input command signal is placed onto said data bus for a single timing signal pulse and thereby in communication with said master controller and for presenting any data from said data bus to said output line for a single timing signal pulse thereby providing a logical output command signal.
Claim 2
Dependent Claim
280 words
A time-slot addressed, system keyed multiplex device, comprising: a master controller (46); a timing signal bus (108) having a continuous series of timing signal pulses (48) thereon, said bus being in communication with the master controller; a data bus (108) in communication with the master controller; at least one logic package (52) having a unique address code (A3, A4, A5, A6, A7, A8), said package in communication with said timing signal bus and said data bus, and being characterized by: a timing circuit (U2, U5/B) having an input connected to receive a timing signal (MCK) on said timing signal bus and producing an output signal representative of the number of timing signal pulses (U3, U4); comparator means (U5/A, U6) adapted to compare said output signal of said timing circuit with a predetermined address code thereby producing a comparator means output signal (Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7) when said output signal of said timing circuit is equal to the address code; an input line (RE1, RE2, RE3, REIn for receiving a logical input command signal from an external device and/or load (32); an output line (Cl, C2, C3, C4) for providing a logical output command signal to an external device and/or load; and logic gating means (U8, U10, U12, U13) adapted to receive said comparator means output signal such that upon receiving said comparator means output signal said logical input command signal is placed onto said data bus for a single timing signal pulse and thereby in communication with said master controller and for presenting any data from said data bus to said output line for a single timing signal pulse thereby providing a logical output command signal.
Claim 3
Dependent Claim
17 words
A device according to claim 1 further characterized in that said master controller (46) is a microprocessor.
Claim 4
Dependent Claim
37 words
A device according to claim 1 further characterized in that upon the occurrence of two out of three consecutive timing signal pulses being in a logical one state, said timing circuit (U2) begins to count clock pulses.
Claim 5
Dependent Claim
28 words
A device according to claim 1 further characterized in that the timing circuit is comprised of a one-shot monostable multivibrator (U2) cooperating with an exclusive NOR gate (U5/B).
Claim 6
Dependent Claim
193 words
A time-slot addressed, system keyed multiplex system having a protocol system characterized in that: a master controller (46) provides a clock pulse train on a clock bus; a data bus facilitates the transmission of data; at least one logic circuit means (52) is in electrical communication with said clock bus (108) and said data bus (108) wherein when at least two of any three consecutive pulses which are placed by said master controller (46) onto said clock bus are in a logical one state, a start condition is indicated to said logic circuit such that a counter (U3, U4) begins to count said clock pulses whereby when the number of clock pulses corresponds to a preassigned address number (A3, A4, A5, A6, A7, A8) for said logic circuit, one bit of data (192) which may be entered onto the data bus by the master controller is allowed to be logically gated through said logic circuitry for a period of one clock pulse and in the next clock pulse allows one bit of data (194) which may be presented to said logic circuit to be placed onto said data bus for one clock pulse.
Claim 7
Dependent Claim
193 words
A time-slot addressed, system keyed multiplex system having a protocol system characterized in that: a master controller (46) provides a clock pulse train on a clock bus; a data bus facilitates the transmission of data; at least one logic circuit means (52) is in electrical communication with said clock bus (108) and said data bus (108) wherein when at least two of any three consecutive pulses which are placed by said master controller (46) onto said clock bus are in a logical one state, a start condition is indicated to said logic circuit such that a counter (U3, U4) begins to count said clock pulses whereby when the number of clock pulses corresponds to a preassigned address number (A3, A4, A5, A6, A7, A8) for said logic circuit, one bit of data (192) which may be entered onto the data bus by the master controller is allowed to be logically gated through said logic circuitry for a period of one clock pulse and in the next clock pulse allows one bit of data (194) which may be presented to said logic circuit to be placed onto said data bus for one clock pulse.
Claim 8
Dependent Claim
49 words
A device according to claim 1 wherein data which is gated through said logic circuit from said master controller appears on a command line (C1, C2, C3, C 4 ) and data which is presented to said master controller is presented over a response line (RE1, RE2, RE3, RE4).
References Cited (Backward Citations)
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