EP0150522A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data processing system with hierarchical memory protection
Assignee: EMC Corp
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Filing: 1981-04-27
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Granted: —
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Expires: 2001-04-27
Abstract
Abstract 32-bit logical addresses (LAO-31) on an address bus (26) include three bits (LA1-3) whose decimal values 0 to 7 define a hierarchy of address regions or rings of decreasing level of protection. Memory protection includes the constraint that a user effectivelv residina in anv ring is derived access to all lower numbered rings. Ring protection logic (111) compares the said three bits (LA1-3) of an address with three bits (CRE1-3) identifying the previously-selected ring. If the comparison shows a jump to a lower ring, protection logic (110) prohibits the memory access.
Inventors
- 👤 Carl J. Alsing
- 👤 Carl Henry
- 👤 Kenneth D. Holberger
- 👤 Charles J. Holland
- 👤 Steven M. Staudaher
- 👤 Steven Wallach
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 19:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30196; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1009; G06F12/14; G06F12/1458; G06F12/1491; G06F9/30189; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/106
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
212 words
A data processing system which utilizes memory storage means (16) for storing a plurality of different groups of data, said memory storage means being capable of storing said different groups of data at different designated locations thereof, characterised in that the designated locations are identifiable (SEGMENT, LAl-3) as storage segment locations having a descending order of protection with respect to data reference accesses by an operator, the addresses of data in each group thereof having a plurality of selected segment bits (LAl-3) which identify the storage segment location in which said data is stored, and by means (111 Fig 4) for responding to the selected segment bits of an address which identify the storage segment locations at which a data reference access is requested to compare the selected segment bits with a plurality of previously selected segment bits (CREl-3) which identify the storage segment location at which a requested data reference access has already been provided with respect to a preceding address; and means (110) responsive to the comparing means (111) for prohibiting a data reference access to an address at a storage segment location which the selected segment bits identify as a segment location having a lower order of protection than the segment location identified by the previously selected segment bits.
Claim 2
Dependent Claim
212 words
A data processing system which utilizes memory storage means (16) for storing a plurality of different groups of data, said memory storage means being capable of storing said different groups of data at different designated locations thereof, characterised in that the designated locations are identifiable (SEGMENT, LAl-3) as storage segment locations having a descending order of protection with respect to data reference accesses by an operator, the addresses of data in each group thereof having a plurality of selected segment bits (LAl-3) which identify the storage segment location in which said data is stored, and by means (111 Fig 4) for responding to the selected segment bits of an address which identify the storage segment locations at which a data reference access is requested to compare the selected segment bits with a plurality of previously selected segment bits (CREl-3) which identify the storage segment location at which a requested data reference access has already been provided with respect to a preceding address; and means (110) responsive to the comparing means (111) for prohibiting a data reference access to an address at a storage segment location which the selected segment bits identify as a segment location having a lower order of protection than the segment location identified by the previously selected segment bits.
Claim 3
Dependent Claim
139 words
A system in accordance with claim 1, characterised in that the comparing means (111) includes means for providing a plurality of selected segment bits which correspond to the selected segment bits of an accessed address which identify the storage segment in which the data reference corresponding to the accessed address is stored; means responsive to the segment bits of an accessed address and to the segment bits of the next address to be accessed to determine the order of protection of the storage segment of said next address relative to the previously accessed address to provide a segment control signal (MAX ERR) when said next address corresponds to a data reference stored in a storage segment location having a lower order of protection than the storage segment location of a data reference at the previously accessed address (Fig 6).
Claim 4
Dependent Claim
90 words
A system in accordance with claim 2,-characterised in that the data reference access prohibiting means (110) includes means responsive to said segment control signal for producing a coded error protection signal (MAX ERR DEF ERR) which indicates that the data reference at the next address is in a storage segment location which is prohibited from access; and means (FAULT CODE ENCODER) responsive to the coded error signal for producing a coded fault signal identifying that a specified fault has occurred due to the presence of the coded error protection signal.
Claim 5
Dependent Claim
122 words
A system in accordance with claim 1, characterised by means (110, 111) for providing access to data references in a current storage segment; means for providing program control instructions which call for access to subroutines stored in a storage segment location different from the storage location currently being used for data references; means (Fig 16) responsive to the program control instructions for determining whether a specified called storage segment in which a subroutine is located has a higher order of protection than the current storage segment; and means (Fig 17) further responsive to the program control instruction when the called storage segment has the higher order of protection for providing entry into the called storage segment and access to a subroutine therein.
Claim 6
Dependent Claim
33 words
A system in accordance with claim 4, characterised by means for indicating a subroutine call fault condition when the called storage segment has a lower order of protection than the current storage segment.
Claim 7
Dependent Claim
95 words
A system in accordance with claim 4, characterised by means for providing a program control instruction which requires a return from operation with respect to a called storage segment to operation with respect to a previously used current storage segment; means for determining whether the previously used current storage segment has a lower order of protection than the called storage segment; and means responsive to a return address in the previously used current storage segment for providing access to the return address when the previously used current storage segment has the lower order of protection.
Claim 8
Dependent Claim
34 words
A system in accordance with claim 6, characterised by means for indicating a return fault condition when the previously used current storage segment has a higher order of protection than the called storage segment.
Claim 9
Dependent Claim
152 words
A system in accordance with claim 4, characterised in that the entry providing means includes means responsive to the program control instruction to provide a branch address including a first field (SBR, P.50) identifying the called storage segment and a second field (GATE NUMBER) specifying a coded gate number; the called storage segment having a storage location which identifies an array of gate numbers resident in the called storage segment; means for comparing the coded gate numbers of the branch address with the maximum gate number resident in the called storage segment; means for permitting the entry into the called storage segment and access to the aubroutine therein when the coded gate number is less than the maxmn gate number. 9. A system in accordance with claim 8, characterised by means for indicating a call fault condition when the coded gate number is equal to or greater than the maximum gate number.
Claim 10
Dependent Claim
154 words
A data processing system having a main memory (16) containing a plurality of segment storage regions, characterised by a plurality of memory management registers (SBR) each associated with one of the segment storage regions and capable of storing a 32-bit double word, the memory management registers being located externally (ATU 14) of the main memory; accumulator storage means for storing a starting address of a block of double words stored in main memory; instruction decode means responsive to one instruction requiring the storage of the block of data words into the memory management system for providing selected control signals; means responsive to the selected control signals for accessing the first word of the block of double words at the starting address in the main memory and for loading the double words in the block into the plurality of memory management registers, the double words being loaded sequentially into the registers in a preselected order.
Claim 11
Dependent Claim
154 words
A data processing system having a main memory (16) containing a plurality of segment storage regions, characterised by a plurality of memory management registers (SBR) each associated with one of the segment storage regions and capable of storing a 32-bit double word, the memory management registers being located externally (ATU 14) of the main memory; accumulator storage means for storing a starting address of a block of double words stored in main memory; instruction decode means responsive to one instruction requiring the storage of the block of data words into the memory management system for providing selected control signals; means responsive to the selected control signals for accessing the first word of the block of double words at the starting address in the main memory and for loading the double words in the block into the plurality of memory management registers, the double words being loaded sequentially into the registers in a preselected order.
References Cited (Backward Citations)
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