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EP0150449A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data processing device

Assignee: Hitachi Microcomputer System Ltd
•
Filing: 1984-12-19
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Granted: —
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Expires: 2004-12-19
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Abstract

Abstract @ Herein disclosed is a data processing device which is equipped with a plurality of arithmetic units so that a plurality of instructions may be processed in parallel by the plural arithmetic units. The data processing device includes: a plurality of physical registers for holding the processed results of the arithmetic units; means for holding the corresponding relationship between logical registers assigned by the instructions and the physical registers; and conversion means for assigning the plural instructions to said arithmetic units and for assigning the different physical registers in a manner to correspond to the logical registers in the respective instructions, when the instructions designated by an identical one of said logical registers are present in plurality in the instructions to be parallel-processed, to hold the assigned physical registers in said holding means. Said arithmetic units hold the processed results in the physical registers held in said holding means.

Inventors

  • 👤 Yooichi Shintani
  • 👤 Tohru Shonai
  • 👤 Shigeo Takeuchi

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 04:08
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8092

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 87 words
A data processing device comprising: a plurality of arithmetic units (Ei)-for processing a plurality of instructions in parallel; a plurality of registers (6, P k )for storing both data to be processed by said arithmetic units and the processed results of said arithmetic units; and control means (3, 4) for assigning the different ones of said registers, respectively, to the instructions which designate an identical register (P k ) and which are present in plurality in the instructions to be processed in parallel in said arithmetic units.
Claim 2
Dependent Claim 87 words
A data processing device comprising: a plurality of arithmetic units (Ei)-for processing a plurality of instructions in parallel; a plurality of registers (6, P k )for storing both data to be processed by said arithmetic units and the processed results of said arithmetic units; and control means (3, 4) for assigning the different ones of said registers, respectively, to the instructions which designate an identical register (P k ) and which are present in plurality in the instructions to be processed in parallel in said arithmetic units.
Claim 3
Dependent Claim 106 words
A data processing device comprising: a plurality of arithmetic units (Ei) for processing a plurality of instructions in parallel; a plurality of physical registers (6, P1) for storing both data to be processed by said arithmetic units and the processed results of said arithmetic units; a control circuit (3, 4) for assigning the different ones of said physical registers, respectively, to the instructions which designate an identical logical register and which are present in plurality in the instructions to be processed in parallel in said arithmetic units; and means for holding the corresponding relationship between said logical register and said assigned physical registers(6, P k ).
Claim 4
Dependent Claim 106 words
A data processing device comprising: a plurality of arithmetic units (Ei) for processing a plurality of instructions in parallel; a plurality of physical registers (6, P1) for storing both data to be processed by said arithmetic units and the processed results of said arithmetic units; a control circuit (3, 4) for assigning the different ones of said physical registers, respectively, to the instructions which designate an identical logical register and which are present in plurality in the instructions to be processed in parallel in said arithmetic units; and means for holding the corresponding relationship between said logical register and said assigned physical registers(6, P k ).

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