Display interface apparatus

Claim 3

The apparatus of Claim 1 wherein the second visual display data are supplied to the visual display by way of a video signal path, and further wherein the combining means include logic means positioned in the video signal path for receiving the first visual display data and the second visual display data and for logically combining the first visual display data with the second visual display data, so that the combined first and second visual display data are supplied on the video signal path to the visual display.

Claim 4

The apparatus of Claim 2, wherein the logic means logically OR's the first and second visual display data.

Claim 5

The apparatus of Claim 3 further including means for controlling the application of the first visual display data and the second visual display data to the logic means so that the output of the logic means can be selected to include solely the first visual display data, solely the second visual display data, or the first visual display data which have been logically OR'ed with the second visual display data.

Claim 6

The apparatus of Claim 3, wherein the logic means comprise OR gate means having a first input connected to receive the first visual display data, a second input connected to receive the second visual display data, and an output connected to the video signal path.

Claim 7

The apparatus of Claim 1, wherein the storage means comprise an addressable memory which is responsive to write addresses and write control signals, and further wherein the first source supplies write address and write control signals in conjunction with the first visual display data so that the first visual display data are stored at the specified addresses in the addressable memory.

Claim 8

The apparatus of Claim 6, wherein the visual display provides a visual image and the first source supplies selected write addresses so that the first visual display data are stored in the addressable memory in a pixel map format, and further wherein the first visual display data stored at a particular address provides attribute information about a portion of the visual image to be produced on the visual display.

Claim 9

The apparatus of Claim 1, wherein the visual display control signals include a vertical sync signal, a horizontal sync signal, and a dot clock, and the access signals include access addresses and access control signals, and further wherein the storage means are responsive to the access addresses and the access control signals received from the generating means so as to supply the visual display data stored at the received access address when the access control signals indicate that an access is permitted, and wherein the generating means include counting means responsive to the dot clock, and the vertical sync signal for maintaining a count which is incremented in accordance with the dot clock and is reset in accordance with the vertical- sync signal, wherein the access addresses comprise the count from the counting means.

Claim 10

The apparatus of Claim 8, wherein the visual image of the visual display is collectively formed from a plurality of parallel scan lines, each scan line comprising a predetermined number of pixels of active video and retrace segments, and further wherein the counting means comprise first counter means responsive to the dot clock for counting up to a quantity corresponding to the predetermined number of pixels and retrace segments in each scan line, wherein the count is automatically reset when the predetermined number is reached; and second counter means coupled to the first" counter means and responsive to the vertical sync signal for counting the number of times the first counter means reaches the predetermined number, wherein the count in the second counter means is reset in accordance with the vertical sync signal, whereby the count from the first counter means provides the portion of the access address by which data for pixels of each scan line are addressed, and the count from the second counter means provides the portion of the access address by which the particular scan line is addressed in the storage means.

Claim 11

The apparatus of Claim 9, wherein the first counter means further include means responsive to the horizontal sync signal for initializing the count in the first counter means in conjunction with the vertical sync signal.

Claim 12

The apparatus of Claim 8, wherein the visual image of the visual display is collectively formed from a predetermined number of parallel scan lines, each scan line comprising a predetermined number of pixels of active video and retrace segments, and further wherein the counting means comprise first counter means responsive to the dot clock for counting up to a quantity corresponding to the predetermined number of pixels and retrace segments in each scan line and for providing an output upon each occurrence of a selected number of dot clock pulses, wherein the count is automatically reset when the predetermined number is reached; second counter means coupled to the first counter means and responsive to the vertical signal for counting the number of times the first counter means reaches the predetermined number and for providing an output whenever the count corresponds to the predetermined number of parallel scan lines, wherein the count in the second counter means is reset in accordance with the vertical sync signal; and third counter means coupled to the first andsecond counter means for maintaining a count which is incremented upon each output from the first counter means and is reset upon each output from the second counter means, wherein the count of the third counter means provide the access address.