Data memory with simultaneous write and read

Claim 3

A binary storage memory structure operable for simultaneously writing and reading data associated with the same word positions comprising separate data buses (18, 22) operable to provide separate data paths for the separate write and read functions, means (26, 30, 36, 40) for separately addressing individual word positions for writing and reading, means (44) for comparing write and read addresses to generate a compare signal (46) when the addresses are the same, said apparatus including means (48) connected for response to said compare signal and operable to inhibit the normal read operation of the addressed word position of said register, said apparatus also including means (49, 50, 52) connected for response to said compare signal and operable to enable the incoming write data signals to generate read data signals.

Claim 4

A binary storage memory structure operable for simultaneously writing and reading data associated with the same word positions comprising separate data buses (18, 22) operable to provide separate data paths for the separate write and read functions, means (26, 30, 36, 40) for separately addressing individual word positions for writing and reading, means (44) for comparing write and read addresses to generate a compare signal (46) when the addresses are the same, said apparatus including means (48) connected for response to said compare signal and operable to inhibit the normal read operation of the addressed word position of said register, said apparatus also including means (49, 50, 52) connected for response to said compare signal and operable to enable the incoming write data signals to generate read data signals.

Claim 5

A structure as claimed in Claim 2 wherein said means for comparing write and read addresses comprises a multiple digit comparison circuit having an exclusive OR gate for comparing each bit of the write address with each corresponding bit of the read address, and operable for generating a comparison signal only if outputs are received from all of said exclusive OR gates.

Claim 6

A structure as claimed in Claim 2 wherein said means connected for response to said compare signal and operable to inhibit the normal read operation of the addressed word position of said register is operable to accomplish that function by inhibiting the normal read operation of all of the word positions of said register is operable to accomplish that function by inhibiting the normal read operation of all of the word positions of said register.

Claim 7

A structure as claimed in Claim 4 wherein a separate driver circuit is provided for each read address with a separate read drive line driven by each driver circuit for each read address, and all of said read address driver circuits being connected to receive a compare signal from said comparing means and being operable for inhibition in response to said compare signal.

Claim 8

A structure as. claimed in Claim 2 wherein said means operable in response to said compare signal to enable the incoming write data signals to generate read data signals comprises switching means for coupling corresponding bit elements of the write and read busses.

Claim 9

A structure as claimed in Claim 2 wherein said memory apparatus comprises individual data bit position cells which provide for differential sensing, and wherein said write and read function data busses each include two individual bit lines for each data word bit for carrying the direct and complement values of the data bit being written or read.