EP0149043A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Random access memory
Assignee: International Business Machines Corp
•
Filing: 1984-11-09
•
Granted: —
•
Expires: 2004-11-09
Abstract
Abstract A random access memory comprising cells (125) is rapidly reset (cleared) to a predetermined conditions (e.g. all ones), by providing an appropriate signal on a data-in lead (132), which sets line (135) to "1" (or "0"), providing a signal on fast clear lead (130)wwhich closes switches in a switch bank (138), which sets the bit lines (128) at the level of line (135), and sequentially energizing the word lines (124).
Inventors
- 👤 Frederick Hayes Dill
- 👤 Satish Gupta
- 👤 Peter James Warter
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 19:54
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/20
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
131 words
An integrated circuit random access memory array having a plurality of words, each of said words being arranged in a column of bits connected to a word line, the bits of said words forming rows and having all the bits in each row connected to a bit line, means for addressing each word line and each bit line for writing a selected bit corresponding to the state of the selected bit line, and a sense amplifier for each bit line for sensing the selected bit on readout, the improvement comprising fast reset control means (134, 136, 138) operative to couple a common signal to said bit lines, and upon energizing of a selected word line, all the bits connected to said selected word line are reset to the state of-said signal.
Claim 2
Dependent Claim
131 words
An integrated circuit random access memory array having a plurality of words, each of said words being arranged in a column of bits connected to a word line, the bits of said words forming rows and having all the bits in each row connected to a bit line, means for addressing each word line and each bit line for writing a selected bit corresponding to the state of the selected bit line, and a sense amplifier for each bit line for sensing the selected bit on readout, the improvement comprising fast reset control means (134, 136, 138) operative to couple a common signal to said bit lines, and upon energizing of a selected word line, all the bits connected to said selected word line are reset to the state of-said signal.
Claim 3
Dependent Claim
20 words
An array as claimed in claim 1, wherein said signal is digital having either a logical 1 or 0 state.
Claim 4
Dependent Claim
21 words
An array as claimed in claim 1, arranged as a frame buffer, coupled to an all points addressable raster scan display.
Claim 5
Dependent Claim
19 words
An array as claimed in claim 1, arranged as a page buffer, coupled to an all points addressable printer.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.