EP0148478A2
Expired / Lapsed
EP
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A data processor with control of the significant bit lenghts of general purpose registers
Assignee: Hitachi Ltd
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Filing: 1984-12-20
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Granted: —
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Expires: 2004-12-20
Abstract
Abstract A mode register (41) stores a mode bit for each of the general registers (11), an access circuit (10,40) accesses the general registers and the mode register so that a general register designated by an instruction and a corresponding mode bit are read out together. A data use circuit (30) or a data supply circuit (3) connected to the general registers (11) includes a circuit portion which effectively changes the significant bit length of the data read out of the designated general register (11) of the data to be written into the designated general register (11).
Inventors
- 👤 Shizuo Gotou
- 👤 Toyohiko Kagimasa
- 👤 Seiichi Yoshizumi
- 👤 Yooichi Shintani
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 22:11
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/30038; G06F9/30098; G06F9/30105; G06F9/30112; G06F9/3012; G06F9/30138; G06F9/30181; G06F9/30189
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
238 words
A data processor for performing data processing operations in response to program instructions, comprising: a plurality of general registers, each having a first predetermined bit length; mode signal storage means for holding a plurality of mode signals each indicating a significant bit length for data stored in a respective one of said general registers; mode reading means responsive to a program instruction for reading out of said mode signal storage means at least one mode signal corresponding to one of the general registers designated by the program instruction as one which should be accessed for read-out or write-in of data; data use means connected to said general registers for processing data from one of the general registers designated by a program instruction which requests a read-out of data from the general registers, including means responsive to a first mode signal read out by said mode reading means in response to the program instruction for changing the significant bit length of the data read out from the first general register; and data supply means connected to said general registers for writing data in one of the general registers designated by a program instruction which requests write-in of data in said general registers, including means responsive to a second mode signal read out by said mode reading means in response to the program instruction for changing the significant bit length of the data to be written into the general register.
Claim 2
Dependent Claim
238 words
A data processor for performing data processing operations in response to program instructions, comprising: a plurality of general registers, each having a first predetermined bit length; mode signal storage means for holding a plurality of mode signals each indicating a significant bit length for data stored in a respective one of said general registers; mode reading means responsive to a program instruction for reading out of said mode signal storage means at least one mode signal corresponding to one of the general registers designated by the program instruction as one which should be accessed for read-out or write-in of data; data use means connected to said general registers for processing data from one of the general registers designated by a program instruction which requests a read-out of data from the general registers, including means responsive to a first mode signal read out by said mode reading means in response to the program instruction for changing the significant bit length of the data read out from the first general register; and data supply means connected to said general registers for writing data in one of the general registers designated by a program instruction which requests write-in of data in said general registers, including means responsive to a second mode signal read out by said mode reading means in response to the program instruction for changing the significant bit length of the data to be written into the general register.
Claim 3
Dependent Claim
53 words
A data processor, according to claim 1, further including a main storage, and wherein said data use means includes address generating means for generating a main storage access address based upon the data read out from a general register and having a significant bit length which is dependent upon said first mode signal.
Claim 4
Dependent Claim
207 words
A data processor, according to claim 2, wherein said address generating means includes: first means for generating a plurality of bits of bit value "0" and having a second predetermined bit length, said second predetermined bit length being smaller than said first predetermined bit length; second means connected to said first means and said mode signal storage means for responding to said first mode signal by modifying the most significant part of the data read out of the register so that the most significant part is replaced by the bits of second predetermined bit value "0", when the first mode signal has a first value; third means for adding the data read out from the register and modified by said second means to a displacement part of the instruction; fourth means for responding to the first mode signal by modifying the most significant part of the data generated by the third means and representing the result of the addition so that the most significant part of the data generated by the third means is replaced by the bits of second predetermined bit length and bit value "0" when the first mode signal has said first value, to provide the result of the modification as said access address.
Claim 5
Dependent Claim
216 words
A data processor according to claim 3; wherein said mode reading means further reads a third mode signal corresponding to a third one of the general registers from said mode signal storage means in response to the instruction and said data use means further reads data from a third general register in response to the instruction; wherein said second means further includes means for responding to the third mode signal by replacing the most significant part of the data read out from the third general register by the bits of second predetermined length and bit value "0"; wherein said third means includes means for adding the data read out from the first and third general registers and modified by the second means to the displacement part of the instruction; and wherein said fourth means includes means for responding to the first and third mode signals and modifying the most significant part of the data generated by the third means and forming the result of the addition so that the most significant part of the data generated by the third means is replaced by the second predetermined bit length of bits "0" when either one of the first and third mode signals has said first value, to provide the result of the modification as said access address.
Claim 6
Dependent Claim
132 words
A data processor according to claim 2, wherein said data supply means includes: first means for fetching data of the first predetermined bit length from said main storage based upon the generated access address; second means for receiving the fetched data and generating data comprising the most significant bits of the fetched data and a plurality of bits of second predetermined bit length and having a bit value "0" or a bit value "1" in response to a predetermined condition of the fetched data, placed at the more significant side of the most significant bits of the fetched data; and third means responsive to the second mode signal for selectively providing either the data generated by the second means or the fetched data to said second general register to be written therein.
Claim 7
Dependent Claim
40 words
A data processor according to claim 5, wherein the second means includes means for selectively generating the second predetermined bit number of bits of value "0" or bits of value "1", depending on the sign bit of the fetched data.
Claim 8
Dependent Claim
180 words
A data processor according to clalm 2, wherein said data supply means includes: first means for fetching data of said first predetermined bit length from said main storage based upon the generated access address; second means for receiving the fetched data and performing an arithmetic operation on a part of the first significant bit length of said fetched data to provide first data corresponding to the result of the operation and having the first significant bit length; third means for receiving the most signifiant bits of a third predetermined bit length of said fetched data and performing the arithmetic operation on the most significant bits of the fetched data, to provide data comprising plural bits of the third bit length obtained as a result of the second operation and plural bits of all "0" or "1" of the more signifiant bit side of the plural bits of the third bit length; and fourth means responding to the second mode signal for selectively providing either one of the first and second data to the second general register to be written therein.
Claim 9
Dependent Claim
180 words
A data processor according to clalm 2, wherein said data supply means includes: first means for fetching data of said first predetermined bit length from said main storage based upon the generated access address; second means for receiving the fetched data and performing an arithmetic operation on a part of the first significant bit length of said fetched data to provide first data corresponding to the result of the operation and having the first significant bit length; third means for receiving the most signifiant bits of a third predetermined bit length of said fetched data and performing the arithmetic operation on the most significant bits of the fetched data, to provide data comprising plural bits of the third bit length obtained as a result of the second operation and plural bits of all "0" or "1" of the more signifiant bit side of the plural bits of the third bit length; and fourth means responding to the second mode signal for selectively providing either one of the first and second data to the second general register to be written therein.
Claim 10
Dependent Claim
68 words
A data processor according to claim 7, wherein said data use means further includes means responsive to a first program instruction for reading out the data from the second general register to provide the read out data to the second means as an operand therefor and the most significant part of the third bit length of the read out data to the third means as an operand therefor.
Claim 11
Dependent Claim
71 words
A data processor according to claim 2, further comprising: logical operation means for performing a logical operation on each pair of respective bit of part of the generated access address bits and a respective one of said plurality of mode signals stored in said mode signal storage means; and means for writing data obtained by said logical operation means into said mode signal storage means in response to a program instruction.
Claim 12
Dependent Claim
16 words
A data processor according to claim 9, wherein said logical operation means includes AND operation means.
Claim 13
Dependent Claim
16 words
A data processor according to claim 9, wherein said logical operation means includes OR operation means.
Claim 14
Dependent Claim
29 words
A data processor according to claim 2, further comprising means responsive to an instruction for storing the plurality of mode signals at a location designated by the generated address.
Claim 15
Dependent Claim
39 words
A data processor according to claim 2, further comprising means responsive to the instruction for loading into said mode signal storage means part of data. stored at a location within the main storage designated at the generated address location.
References Cited (Backward Citations)
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