EP0148475A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Logic circuit
Assignee: Fujitsu Ltd
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Filing: 1984-12-19
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Granted: —
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Expires: 2004-12-19
Abstract
Abstract Propagation delay time of a TTL type logic circuit of a Totem pole or an open collector type having a capacitive output load (C L ) is reduced without increasing power consumption, and the propagation delay time is made free from stray capacitance of the output load (C L ) when an output level of the TTL logic circuit changes from high to low. A discharge control transistor (Q 15 ) is connected between an output terminal (To) and a collector of a pre-stage transistor (Q 11 ) for a driving transistor (Q 12 ) whose collector is connected the output terminal (To). The discharge control transistor (Q 15 ) becomes conductive and controls the driving transistor (Q 12 ) so as to pull down charge which has been stored in stray capacity of the output load (C L ) by making base current of the driving transistor (Q 12 ) flow more through the discharge control transistor (Q 15 ) and the pre-stage transistor (Q 11 ), in a limited time during the output of the TTL type logic circuit is changing from a high level to a low level.
Inventors
- 👤 Akinori Tahara
- 👤 Masao Kumagai
- 👤 Hiromu Enomoto
- 👤 Yasushi Yasuda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 23:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/01; H03K19/013; H03K19/0136; H03K19/02; H03K19/08; H03K19/082; H03K19/088
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
238 words
A logic circuit, characterized in an input unit (101) for providing an output level being high or low receiving at least one input logic whose level being high or low; and an output unit (102) for providing an output of said logic circuit so that a level of said output is high or low receiving said output level of said input unit, said output unit (102) further comprising: a driving transistor (Q 12 ' Q 22 ) connected to an output terminal (T O ) of said logic circuit, said output terminal (T O ) being connected to an output load (C L ), for pulling down the output level of said logic circuit from high to low; a pre-stage transistor (Q 11 , Q21) connected between said driving transistor (Q12, Q 22 ) and said input unit (101), for controlling said driving transistor (Q 12 ' Q 22 ) a c cor- ding to said output level of said input unit (101); and a discharge control transistor (Q 15 ' Q 23 ' Q 24 ) connected between said output terminal (T O ) and said pre-stage transistor (Q 11 ' Q 21 ), for controlling said driving transistor (Q11, Q 21 ) so as to discharge the charge having been stored in the stray capacity of said output load (C L ), while the output level of said logic circuit is changing from high to low.
Claim 2
Dependent Claim
238 words
A logic circuit, characterized in an input unit (101) for providing an output level being high or low receiving at least one input logic whose level being high or low; and an output unit (102) for providing an output of said logic circuit so that a level of said output is high or low receiving said output level of said input unit, said output unit (102) further comprising: a driving transistor (Q 12 ' Q 22 ) connected to an output terminal (T O ) of said logic circuit, said output terminal (T O ) being connected to an output load (C L ), for pulling down the output level of said logic circuit from high to low; a pre-stage transistor (Q 11 , Q21) connected between said driving transistor (Q12, Q 22 ) and said input unit (101), for controlling said driving transistor (Q 12 ' Q 22 ) a c cor- ding to said output level of said input unit (101); and a discharge control transistor (Q 15 ' Q 23 ' Q 24 ) connected between said output terminal (T O ) and said pre-stage transistor (Q 11 ' Q 21 ), for controlling said driving transistor (Q11, Q 21 ) so as to discharge the charge having been stored in the stray capacity of said output load (C L ), while the output level of said logic circuit is changing from high to low.
Claim 3
Dependent Claim
232 words
A logic circuit according to claim 1, characterized in that said logic circuit is a Totem pole type circuit having a pull up transistor (Q 13' Q 14 ) connected to said driving transistor (Q 12 ) in series, and a collector of said driving transistor (Q 12 ) is connected to said output terminal and to an emitter of said pull u p transistor (Q 13' Q 14 ) ' and a base of said driving transistor (Q 12 ) is connected to an emitter of said p r e-stage transistor (Q 11 ); said pre-stage transistor is a selective transistor (Q 11 ), and a collector of said selective transistor (Q 11 ) is connected to an emitter of said discharge control transistor (Q 15 ) and to a base of a transistor (Q 13 ) whose emitter is connected to a base of said pull up transistor (Q 14 ) forming a Darlington connection, and a base of said selective transistor (Q 11 ) is connected to said input unit (101); and a collector of said discharge control transistor (Q 15 ) is connected to said output terminal (T O ) through a current blocking diode (D 13 ), and a base of said discharge control transistor (Q 15 ) is connected to the emitter of said transistor (Q 13 ) connected to said pull u p transistor (Q14).
Claim 4
Dependent Claim
206 words
A logic circuit according to claim 1, characterized in that said logic circuit is an open collector type circuit, and a collector of said driving transistor (Q 12 ) is connected to said output terminal (T O ) ' and a base of said driving transistor (Q 22 ) is connected to an emitter of said pre-stage transistor (Q21); . said pre-stage transistor is a phased splitter transistor (Q 21 ), and its base is connected to said input unit (101); and said discharge control transistor comprises a first discharge control transistor (Q 24 ) and a second discharge control transistor (Q 23 ) , a collector of said first discharge control transistor (Q 24 ) is connected to said output terminal (T O ) through a current blocking diode (D 21 ), an emitter of said first discharge control transistor (Q 24 ) is connected to a collector of said phased splitter transistor (Q 21 ), a base of said first discharge control transistor (Q 24 ) is connected to an emitter of said second discharge control transistor (Q 23 ) ' and a base of said second discharge control transistor (Q 23 ) is connected to the collector of said phased splitter transistor (Q21).
Claim 5
Dependent Claim
29 words
A logic circuit according to any one of claims 1 - 3, characterized in that the transistors are Shottky Barrier Transistors and the diode is a Shottky Barrier Diode.
References Cited (Backward Citations)
No citation records indexed.
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