High-speed semiconductor device, in particular a high-voltage p-i-n diode
Abstract
Abstract The device consists of an inner zone, formed by at least one high resistivity silicon layer lying between two outer layers of extrinsic silicon, one above and one below. Both the lower and upper outer layers consist, at least in one active region (11) of the device, of thin layers (P, N). The high resistivity silicon layer (I) lacks additional recombination centres capable of reducing the lifetime of the minority carriers present in this layer during the transition from the conducting state to the cut- off state. The thickness and doping of the outer layers (P, N) are determined by the required level of minority-carrier injection in the conducting phase. <IMAGE>
Inventors
- 👤 Pierre Rossetti
- 👤 Jacques Arnould
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.