Data processing apparatus for processing operand store conflict

Claim 2

A data processing apparatus for processing a store-type instruction which stores an operand as a result of an instruction execution in a storage location of a storage (5) and a fetch-type instruction which fetches an operand from a storage location, comprising: a detecting means (2) for detecting that an execution result of said store-type instruction for which a store operation has not been completed is utilized as an operand of said fetch-type instruction which succeeds said store-type instruction; and a control means (12-1, 12-2, 13-1, 13-2, 14-1, 14-2) for aligning an operand position with the operand fetched by said fetch-type instruction and for merging an store operand in response to a detection by said detecting means and a store operation for storing said execution result.

Claim 3

A data processing apparatus according to Claim 1 wherein said detecting means (2) includes a detect circuit (113-1, 113-2, ... 113-n) which operates based on the first and last addresses of an operand for which a store operation has not been completed by said store-type instruction and the first and last address of an operand contained in said fetch-type instruction for detecting an overlap between the operands.

Claim 4

A data processing apparatus according to Claim 1 wherein said detecting means (2) includes: a plurality of register means (114-1 to 114-n) for storing first and last addresses of operands for said store-type instructions for which store operation has not been completed; and a plurality of OSC detect circuits (113-1 to 113-n) associated with each said register means for detecting an OSC based on said address held in the associated register means and the first and last address of an operand of a fetch-type instruction which succeeds said store-type instructions.

Claim 5

A data processing apparatus according to Claim 3 wherein said detecting means (2) further includes: update means (115-1 to 115-n) for updating said first addresses held in said register means associated with said store-type instructions for which the store operation is executed each time the store operation is executed; and invalidate means (116-1 to 116-n) for invalidating the addresses held in said register means when the first and last address each held in the respective register means becomes equal to each other.

Claim 6

A data processing apparatus according to Claim 3 further comprising arithmetic and logical means (8) for executing an operation specified by said instruction wherein said control means includes: a plurality of operand buffer registers (14-1, 14-2) for holding the operands fetched by different said fetch-type instructions from said storage (5) until said operands are executed by said arithmetic and logical means (8); and a plurality of merge means (12-1, 12-2, 13-1, 13-2) for merging a result from execution of said store-type instruction in said arithmetic and logical means (8) into said operand buffer register (14-1, 14-2) in response to a detection by said detecting means (2) by aligning the result to the operand position held in said operand buffer register (14-1, 14-2).

Claim 7

A data processing apparatus according to Claim 5 wherein said merge means includes a plurality of shift means (12-1, 12-2) each associated with each said operand buffer register (14-1, 14-2) for aligning said execution result to a fetched operand position held in said operand buffer register (14-1, 14-2) on which a merge operation is to be executed.

Claim 8

A data processing apparatus according to Claim 6 wherein said control means (2) further comprises: a plurality of latch means (202-ij) for latching detection results from said plurality of OSC detect circuits (113-1 to 113-n) corresponding to said plurality of operand buffer registers (14-1, 14-2), said latch means (202-ij) provided for latching said plurality of detection results in said latch means associated with said operand buffer registers (14-1, 14-2) to which operands are set in response to a fetch request to said storage (5) by said fetch-type instruction, and said latch means provided further for outputting said detection results associated with said store-type instruction which executes said store operation in response to said store operation; and means (301-1, 301-2) disposed in association with said operand buffer registers (14-1, 14-2) for controlling said merge means (13-1, 13-2) and said operand buffer registers based on the detection result from said latch means (202-ij), information about said store operands, and information about said fetch operands.