Semiconductor memory device

Claim 2

A semiconductor memory device characterized in that said semiconductor memory device comprises: a memory cell array; an addressing circuit which effects an access operation to each bit of said memory cell array in accordance with an external address; an internal address generating circuit which sequentially generates row addresses; an address switching circuit which switches between the row address output from said internal address generating circuit and said external address; a plurality of shift registers each of which stores a plurality bit data parallelly read out from said memory cell array in accordance with said row address; and a serial control circuit which controls said shift registers; said serial control circuit controls each of said shift registers so that each of said shift registers effects shift operation to serially and continuously output data, and when said memory cell array is not accessed by an external circuit during a time period in which plurality bit data corresponding to a row address is serially output from one of said plurality of shift registers, said serial control circuit effects parallel readout operation of plurality bit data corresponding to the next row address from said memory cell array and loads the data thus read out to another shift register.

Claim 3

A semiconductor memory device according to claim 1, wherein the access operation by an external circuit is effected by using said external address and a random access signal, and said address switching circuit switches between the row address output from said internal address generating circuit and an external row address data included in said external address.

Claim 4

A semiconductor memory device according to claim 1, wherein each of said plurality of shift registers effects shift operation in accordance with serial clocks supplied thereto from an external circuit, and said serial control circuit counts said serial clocks to generate increment clocks which are counted by said internal address generating circuit to generate said row address.

Claim 5

A semiconductor memory device according to claim 1, wherein said addressing circuit comprises a row decoder for decoding a row address data output from said address switching circuit and a column decoder for decoding an external column address data included in said external address.

Claim 6

A semiconductor memory device according to claim 4, wherein said external address includes said external column address data and an external row address data, and said external column address data and said external row address data are supplied to said column decoder and said row decoder via a column address buffer and a row address buffer.

Claim 7

A semiconductor memory device according to claim 1, wherein said semiconductor memory device comprises a selecting circuit for selecting one of said shift registers to or from which serial data is input or output, in accordance with a register selecting signal supplied by said serial control circuit.

Claim 8

A semiconductor memory device according to claim 6, wherein said selecting circuit transmits serial output data of said selected one of said shift registers to an external circuit or transmits serial input data from an external circuit to said selected one of said shift registers.

Claim 9

A semiconductor memory device characterized in that said semiconductor memory device comprises: a memory cell array; an addressing circuit which effects an access operation to each bit of said memory cell array in accordance with an external address; an internal address generating circuit which sequentially generates row addresses; an address switching circuit which switches between the row address output from said internal address generating circuit and said external address; a plurality of shift registers each of which stores a plurality bit data to be written-in parallelly to said memory cell array in accordance with said row address; and a serial control circuit which controls said shift registers; said serial control circuit controls each of said shift registers so that each of said shift registers effects shift operation to serially and continuously record data therein, and when said memory cell array is not accessed by an external circuit during a time period in which plurality bit data corresponding to a row address is serially recorded into one of said plurality of shift registers from an external circuit, said serial control circuit effects parallel write-in operation of plurality bit data corresponding to the next row address to said memory cell array.

Claim 10

A semiconductor memory device characterized in that said semiconductor memory device comprises: a memory cell array; an addressing circuit which effects an access operation to each bit of said memory cell array in accordance with an external address; an internal address generating circuit which sequentially generates row addresses; an address switching circuit which switches between the row address output from said internal address generating circuit and said external address; a plurality of shift registers each of which stores a plurality bit data to be written-in parallelly to said memory cell array in accordance with said row address; and a serial control circuit which controls said shift registers; said serial control circuit controls each of said shift registers so that each of said shift registers effects shift operation to serially and continuously record data therein, and when said memory cell array is not accessed by an external circuit during a time period in which plurality bit data corresponding to a row address is serially recorded into one of said plurality of shift registers from an external circuit, said serial control circuit effects parallel write-in operation of plurality bit data corresponding to the next row address to said memory cell array.

Claim 11

A memory system for effecting random access and serial access independently characterized in that said memory system comprises a plurality of semiconductor memory devices and an external shift register having a number of circuit stages equal to that of said semiconductor memory devices, the serial output data from said semiconductor memory devices is parallelly loaded to said circuit stages of said external shift register or data stored in said external shift register is parallelly written-in to said semiconductor memory devices, and said external shift register serially outputs data stored therein or serially records data therein, each of said semiconductor memory devices comprising: a memory cell array; an addressing circuit which effects an access operation to each bit of said memory cell array in accordance with an external address; an internal address generating circuit which sequentially generates row addresses; an address switching circuit which switches between the row address output from said internal address generating circuit and said external address; a plurality of shift registers each of which stores a plurality bit data parallelly read out from or write-in to said memory cell array in accordance with said row address; and a serial control circuit which controls said shift registers; said serial control circuit controls each of said shift registers so that each of said shift registers effects shift operation to serially and continuously output or write-in data, and when said memory cell array is not accessed by an external circuit during a time period in which plurality bit data corresponding to a row address is serially output from or recorded into one of said plurality of shift registers, said serial control circuit effects parallel readout or write-in operation of plurality bit data corresponding to the next row address from or to said memory cell array.

Claim 12

A memory system for effecting random access and serial access independently characterized in that said memory system comprises a plurality of semiconductor memory devices and an external shift register having a number of circuit stages equal to that of said semiconductor memory devices, the serial output data from said semiconductor memory devices is parallelly loaded to said circuit stages of said external shift register or data stored in said external shift register is parallelly written-in to said semiconductor memory devices, and said external shift register serially outputs data stored therein or serially records data therein, each of said semiconductor memory devices comprising: a memory cell array; an addressing circuit which effects an access operation to each bit of said memory cell array in accordance with an external address; an internal address generating circuit which sequentially generates row addresses; an address switching circuit which switches between the row address output from said internal address generating circuit and said external address; a plurality of shift registers each of which stores a plurality bit data parallelly read out from or write-in to said memory cell array in accordance with said row address; and a serial control circuit which controls said shift registers; said serial control circuit controls each of said shift registers so that each of said shift registers effects shift operation to serially and continuously output or write-in data, and when said memory cell array is not accessed by an external circuit during a time period in which plurality bit data corresponding to a row address is serially output from or recorded into one of said plurality of shift registers, said serial control circuit effects parallel readout or write-in operation of plurality bit data corresponding to the next row address from or to said memory cell array.