EP0147203A2
Expired / Lapsed
EP
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Method of forming multilayer interconnections for a semiconductor device
Assignee: Toshiba Corp
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Filing: 1984-12-20
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Granted: —
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Expires: 2004-12-20
Abstract
Abstract A method of forming a multilayer interconnection for a semiconductor device comprising a first insulation layer (12) deposited on a substrate (11) having semiconductor elements, first interconnection patterns (13), a second insulation layer (14) interposed between the first interconnection patterns (13), a third insulation layer (16) covering the first interconnection patterns (13) and second interconnection patterns (18) contacted with the first interconnection patterns (13), wherein the first interconnection patterns (13) are formed in such a manner that the first interconnection patterns (13) cover both edges of the interposed second insulation layer (14).
Inventors
- 👤 Yoshikazu C/O Patent Division Hazuki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 10:09
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/40; H10W20/41; H10W20/42; Y; Y10; Y10S; Y10S148/00; Y10S148/019; Y10S148/026
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
140 words
A method of forming multilayer interconnections for a semiconductor device comprising-the steps of: (i) forming a first insulation layer on a substrate having semiconductor elements; (ii) forming first interconnection patterns with a second insulation layer interposed between the patterns of the first interconnection; (iii) forming a third insulation layer at least on the first interconnection patterns; (iv) forming a hole in said third insulation layer to expose part of said first interconnection patterns; and (v) forming second interconnection patterns so as to be brought into contact with said first interconnection patterns through said hole, the second interconnection patterns overlapping the first interconnection patterns; characterized in that in step (ii) a second insulation layer is interposed between the patterns of the first interconnection in such a manner that said first interconnection patterns cover edge part of said interposed second insulation layer.
Claim 2
Independent Claim
140 words
A method of forming multilayer interconnections for a semiconductor device comprising-the steps of: (i) forming a first insulation layer on a substrate having semiconductor elements; (ii) forming first interconnection patterns with a second insulation layer interposed between the patterns of the first interconnection; (iii) forming a third insulation layer at least on the first interconnection patterns; (iv) forming a hole in said third insulation layer to expose part of said first interconnection patterns; and (v) forming second interconnection patterns so as to be brought into contact with said first interconnection patterns through said hole, the second interconnection patterns overlapping the first interconnection patterns; characterized in that in step (ii) a second insulation layer is interposed between the patterns of the first interconnection in such a manner that said first interconnection patterns cover edge part of said interposed second insulation layer.
Claim 3
Dependent Claim
67 words
The method according to claim 1, characterized - in that said step (ii) involves the substeps of: (a) embedding the second insulation layer between the first interconnection patterns to expose the upper surface of the respective first interconnection; and (b) depositing a metal layer or metal silicide layer on the first interconnection patterns by a selective vapor phase growth process using a gas of a metal compound.
Claim 4
Dependent Claim
32 words
The method according to claim 1, characterized in that said step (ii) involves the substep of forming the first interconnection patterns so as to cover edge parts of interposed second insulation layer.
Claim 5
Dependent Claim
27 words
4 . The method according to claim 2, characterized in that said metal is one selected from the group consisting of tungsten, molybdenum, niobium, tantalum and titanium.
Claim 6
Dependent Claim
85 words
The method according to claim 2, characterized in that said substep (a) involves the process of depositing a silicon oxide layer by the vapor growth method on the whole of the first interconnection pattern prepared from an aluminium layer in said step (ii), later forming a silicon nitride layer on said silicon oxide layer, and etching said silicon oxide layer and silicon nitride layer by the reactive ion etching process involving the application of a gas mixture consisting of CF 4 and H 2 .
Claim 7
Dependent Claim
96 words
The method according to claim 1, characterized in that said step (ii) comprises the substeps of: forming a second insulation layer on a substrate in which said first insulation layer is previously deposited; selectively etching said second insulation layer, thereby forming a groove or hole in that region of said second insulation layer where said first interconnection is to be formed; and embedding an electrically conductive material in said groove or hole by the selective vapor phase growth process with a thickness greater than the depth of said groove or hole, thereby forming a first interconnection.
Claim 8
Dependent Claim
56 words
The method according to claim 6, characterized in that the step of forming said first interconnection is represented by the deposition of a high melting metal layer to provide said electrically conductive material by the vapor phase growth process involving the application of a gas consisting of the fluoride or chloride of a high melting metal.
Claim 9
Dependent Claim
59 words
The method according to claim 6, characterized in that the step of forming said first interconnection is represented by the deposition of a high melting metal layer to provide said electrically conductive material by the vapor phase growth process involving the application of a gaseous mixture consisting of the fluoride, a chloride of a high melting metal and silicon.
Claim 10
Dependent Claim
30 words
9 . The method according to claim 6, characterized in that the surface of the bottom of said groove is activated prior to the step of forming said first interconnection.
Claim 11
Dependent Claim
28 words
The method according to claim 6, characterized in that the second insulation layer is selectively etched by the reactive ion etching process to provide said groove or hole.
Claim 12
Dependent Claim
28 words
The method according to claim 9, characterized in that said activation of the surface of the bottom of the groove is carried out by the irradiation of electrons.
Claim 13
Dependent Claim
28 words
The method according to claim 9, characterized in that said activation of the surface of the bottom of the groove is effected by the irradiation of laser beams.
References Cited (Backward Citations)
No citation records indexed.
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