EP0147151A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory with stacked structure
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1984-12-17
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Granted: —
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Expires: 2004-12-17
Abstract
Abstract A three-transistor random access memory cell has two transistors (T 2 , T 3 ) formed in a semiconductor substrate (1), with the source or drain (3) of one transistor being connected to the source or drain of the other transistor. Another transistor (T 1 ) of the cell is stacked on one of the transistors (T 3 ) in the substrate (1) with its source or drain (12) connected to the gate of the other transistor (T 2 ) in the substrate. The stacking of one transistor (T 1 ) on another (T 3 ) reduces the area occupied by the device and so permits- extremely large scare integration.
Inventors
- 👤 Hitoshi Kume
- 👤 Takaaki Hagiwara
- 👤 Masatada Horiuchi
- 👤 Toru Kaga
- 👤 Yasuo Igura
- 👤 Akihiro Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 13:05
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; H; H10; H10B; H10B12/00; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
89 words
A semiconductor memory having three transistors (T 1 , T 2 , T 3 ), the drain or source (12) of the first transistor (T 1 ) being connected to the gate (8) of the second transistor (T 2 ), and the drain or source (3) of the second transistor (T 2 ) being connected to the drain or source (3) of the third transistor (T 3 ); characterised in that: at least a part of the first transistor (T1) is stacked on the third transistor (T 3 ).
Claim 2
Dependent Claim
89 words
A semiconductor memory having three transistors (T 1 , T 2 , T 3 ), the drain or source (12) of the first transistor (T 1 ) being connected to the gate (8) of the second transistor (T 2 ), and the drain or source (3) of the second transistor (T 2 ) being connected to the drain or source (3) of the third transistor (T 3 ); characterised in that: at least a part of the first transistor (T1) is stacked on the third transistor (T 3 ).
Claim 3
Dependent Claim
32 words
A semiconductor memory according to claim 1, wherein the source or drain (10) of the first transistor (T 1 ) is connected to the source or drain (2) of the third transistor.
Claim 4
Dependent Claim
73 words
A semiconductor memory according to claim 1 or claim 2, wherein the drain or source (12) of the first transistor (T 1 ) is connected to the gate (8) of the second transistor (T 2 ) by a semiconductor layer formed in the same production step as the formation of the gate (8) of the second transistor (T 2 ) and the drain or source (12) of the first transistor (T 1 ).
Claim 5
Dependent Claim
33 words
A semiconductor memory according to claim 1 or claim 2, wherein the gate electrodes of the second and third transistors (T 2 , T 3 ) are formed in the same production step.
Claim 6
Dependent Claim
59 words
A semiconductor memory according to any one of claims 2 to 4, wherein a region connecting the source or drain (10) of the first transistor (T 1 ) to the source or drain (2) of the third transistor is a data input part, and the source or drain of the second transistor (T 2 ) receives a reference potential.
References Cited (Backward Citations)
No citation records indexed.
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