Patent US4066469A successfully refreshed from Google Patents.
EP0146293A1
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EP
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Time-slot interchanger for fast circuit switching
Assignee: AT&T Inc
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Filing: 1984-11-30
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Granted: —
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Expires: 2004-11-30
Abstract
Abstract @ A fast circuit switching system that establishes a circuit for each packet-sized data communication. A time-slot interchanger (5100) included in the system network (5000) has a sequential access, circulating control memory (5445), the contents of which can be rapidly and frequently changed with minimal impairment of time-slot interchanger throughput. Such changes are effected by controlling the transmission of information concerning established connections, from a control memory output register (5446-31) to a control memory input register (5446-0) and by controlling the transmission of information concerning new connections, to the control memory input register.
Inventors
- 👤 Milo Orsic
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 21:54
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04L; H04L49/00; H04L49/10
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
158 words
An arrangement comprising a plurality of input storage locations for storing digital words, a plurality of output storage locations for storing digital words, control memory input path means for sequentially receiving connection words each defining one of said input storage locations and one of said output storage locations, control memory means for storing, for at most a predetermined duration, each of said connection words received by said control memory input path means, transfer means coupled to said control memory means and responsive to said connection words stored by said control memory means, for transferring digital words stored in ones of said input storage locations, to ones of said output storage locations as defined by those connection words and first enable gate means also coupled to said control memory means, for selectively transmitting ones of said connection words stored by said control memory means, to said control memory input path means for storage again by said control memory means.
Claim 2
Dependent Claim
158 words
An arrangement comprising a plurality of input storage locations for storing digital words, a plurality of output storage locations for storing digital words, control memory input path means for sequentially receiving connection words each defining one of said input storage locations and one of said output storage locations, control memory means for storing, for at most a predetermined duration, each of said connection words received by said control memory input path means, transfer means coupled to said control memory means and responsive to said connection words stored by said control memory means, for transferring digital words stored in ones of said input storage locations, to ones of said output storage locations as defined by those connection words and first enable gate means also coupled to said control memory means, for selectively transmitting ones of said connection words stored by said control memory means, to said control memory input path means for storage again by said control memory means.
Claim 3
Dependent Claim
75 words
An arrangement in accordance with claim 1 further comprising new connection word storage means for storing new connection words each defining one of said input storage locations and one of said output storage locations and second enable gate means coupled to said new connection word storage means, for transmitting said new connection words stored by said new connection word storage means, to said control memory input path means for storage by said control memory means.
Claim 4
Dependent Claim
61 words
An arrangement in accordance with claim 2 further comprising means for controlling said second enable gate means such that said new connection words stored by said new connection word storage means, are transmitted to said control memory input path means during times when no connection words stored by said control memory means, are being transmitted by said first enable gate means.
Claim 5
Dependent Claim
92 words
An arrangement in accordance with claim 3 further comprising a plurality of disconnect memory locations each associated with one of said output storage locations, for storing disconnect signals and inhibit means coupled to said disconnect memory locations, for inhibiting the transmission by said first enable gate means of a given one of said connection words stored by said control memory means, when one of said disconnect signals is stored in the one of said disconnect memory locations associated with the one of said output storage locations defined by that given connection word.
Claim 6
Dependent Claim
138 words
An arrangement in accordance with claim 4 wherein said control memory means comprises input register means, output register means and a plurality of intermediate register means connected in series between said input register means and said output register means, wherein said input register means is connected to receive connection words from said control memory input path means and to transmit connection words to a first one of said intermediate register means, wherein said output register means is connected to receive connection words from a last one of said intermediate register means and to transmit connection words to said first enable gate means and wherein said arrangement further comprises means for shifting each connection word received by said control memory input path means through said input register means, said plurality of intermediate register means and said output register means.
Claim 7
Dependent Claim
79 words
An arrangement in accordance with claim 5 wherein said transfer means comprises means coupled to said last intermediate register means for reading digital words from ones of said input storage locations defined by the connection words shifted to said last intermediate register means and means coupled to said output register means for writing digital words read from said input storage locations, into ones of said output storage locations defined by the connection words shifted to said output register means.
Claim 8
Dependent Claim
108 words
An arrangement in accordance with claim 5 further comprising disconnect memory reading means connected to said last intermediate register means for reading the ones of said disconnect memory locations defined by the connection words shifted to said last intermediate register means and disconnect register means for temporarily storing disconnect signals read from ones of said disconnect memory locations by said disconnect memory reading means and wherein said inhibit means inhibits the transmission by said first enable gate means of the connection words shifted to said output register means, whenever one of said disconnect signals read by said disconnect memory reading means is present in said disconnect register means.
Claim 9
Dependent Claim
81 words
An arrangement in accordance with claim 4 further comprising disconnection word storage means for storing disconnection words each defining one of said output storage locations, bus means for transmitting said disconnection words stored in said disconnection word storage means and means responsive to each of said disconnection words transmitted by said bus means, for storing a disconnect signal in one of said disconnect memory locations that is associated with the one of said output storage locations defined by that disconnection word.
Claim 10
Dependent Claim
99 words
An arrangement in accordance with claim 4 further comprising third enable gate means for transmitting null words to said control memory input path means for storage by said control memory means and means for controlling said third enable gate means such that ones of said null words are transmitted to said control memory input path means during times when no connection words stored by said control memory means are being transmitted by said first enable gate means and no new connection words stored by said new connection word storage means are being transmitted by said second enable gate means.
Claim 11
Dependent Claim
92 words
An arrangement in accordance with claim 1 further comprising a plurality of disconnect memory locations each associated with one of said output storage locations, for storing disconnect signals and inhibit means coupled to said disconnect memory locations, for inhibiting the transmission by said first enable gate means of a given one of said connection words stored by said control memory means, when one of said disconnect signals is stored in the one of said disconnect memory locations associated with the one of said output storage locations defined by that given connection word.
References Cited (Backward Citations)
US4038497A
Cited
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